On Thu, Aug 03, 2023 at 12:13:00PM +0100, Mark Rutland wrote: [...] > However, in looking at it I think > there may me a wider potential isssue w.r.t. the way instruction memory gets > reused, because as writtten today the architecture doesn't seem to have a > guarantee on when instruction fetches are completed and therefore when it's > safe to modify instruction memory. Usually we're saved by TLB maintenance, > which this series avoids by design. Just to confirm on this point specifically, per discussions with our architects, the (architectural) execution of an instruction ensures that there are no outstanding fetches for prior instructions. IIUC that will be clarified the next release of the ARM ARM. So as long as we're certain all threads have left the old code (e.g. via a flag, RCU tasks rude synchronization, whatever) before we overwrite slots in the shared buffer, we should be good. We will need to be very careful with the maintenance when installing new code into the shared buffer (e.g. we will require an IPI to all other CPUs), but that should be relatively simple. I'll go review the latest patches with that in mind. Thanks, Mark.
