Luke Nelson writes:
<snip>
> +
> +static int emit_insn(const struct bpf_insn *insn,
> + struct rv_jit_context *ctx,
> + bool extra_pass)
> +{
> + int rvoff, i = insn - ctx->prog->insnsi;
> + u8 code = insn->code;
> + s16 off = insn->off;
> + s32 imm = insn->imm;
> +
> + const s8 *dst = bpf2rv32[insn->dst_reg];
> + const s8 *src = bpf2rv32[insn->src_reg];
> + const s8 *tmp1 = bpf2rv32[TMP_REG_1];
> + const s8 *tmp2 = bpf2rv32[TMP_REG_2];
> +
> + switch (code) {
> + case BPF_ALU64 | BPF_MOV | BPF_X:
> + if (imm == 1) {
> + /* Special mov32 for zext */
> + emit_rv32_zext64(dst, ctx);
> + break;
> + }
Thanks for adding the 32-bit opt!
Just want to mention ZEXT is a special mov32, see include/linux/filter.h:
#define BPF_ZEXT_REG(DST)
((struct bpf_insn) {
.code = BPF_ALU | BPF_MOV | BPF_X
So it can't be BPF_ALU64. It is safe to remove this chunk of code.
For backend like arm, riscv etc, they are grouping several CASE label
together and are sharing code. imm == 1 check is done inside the shared
code to avoid moving code around given imm == 1 can't be true for ALU64 as
if there is such insn (register format using imm) it should have been
rejected by verifier. While mov32 variant is inserted by verifier at very
late stage after main verification finished.
Regards,
Jiong
