From: Aric Cyr <aric.cyr@xxxxxxx> Acked-by: Hersen Wu <hersenxs.wu@xxxxxxx> Signed-off-by: Aric Cyr <aric.cyr@xxxxxxx> Summary: - Enable DCN35 physymclk root clock gating - Fix DP automation test pattern bug - Disable OTG for mode switch from TMDS to FRL - Refactor DML2 - Revert Fix handling duplicate planes on one stream - Revert Enable DCN clock gating - Implement cursor P-State allow for SubVP - Optimize pipe otg allocation - Save and restore mall state while switching from ODM to Subvp --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 09328f1670aa..c5e7da302acb 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -49,7 +49,7 @@ struct aux_payload; struct set_config_cmd_payload; struct dmub_notification; -#define DC_VER "3.2.258" +#define DC_VER "3.2.259" #define MAX_SURFACES 3 #define MAX_PLANES 6 -- 2.25.1
