On Wed, Nov 1, 2023 at 5:02 AM Tim Huang <Tim.Huang@xxxxxxx> wrote:
>
> Use a proper MEID to make sure the CP_HQD_* and CP_GFX_HQD_* registers
> can be touched when initialize the compute and gfx mqd in mes_self_test.
> Otherwise, we expect no response from CP and an GRBM eventual timeout.
>
> Signed-off-by: Tim Huang <Tim.Huang@xxxxxxx>
Acked-by: Alex Deucher <alexander.deucher@xxxxxxx>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 16 ++++++++++++++++
> 1 file changed, 16 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
> index 70fe3b39c004..5ff76163ea27 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
> @@ -556,8 +556,20 @@ static void amdgpu_mes_queue_init_mqd(struct amdgpu_device *adev,
> mqd_prop.hqd_queue_priority = p->hqd_queue_priority;
> mqd_prop.hqd_active = false;
>
> + if (p->queue_type == AMDGPU_RING_TYPE_GFX ||
> + p->queue_type == AMDGPU_RING_TYPE_COMPUTE) {
> + mutex_lock(&adev->srbm_mutex);
> + amdgpu_gfx_select_me_pipe_q(adev, p->ring->me, p->ring->pipe, 0, 0, 0);
> + }
> +
> mqd_mgr->init_mqd(adev, q->mqd_cpu_ptr, &mqd_prop);
>
> + if (p->queue_type == AMDGPU_RING_TYPE_GFX ||
> + p->queue_type == AMDGPU_RING_TYPE_COMPUTE) {
> + mutex_unlock(&adev->srbm_mutex);
> + amdgpu_gfx_select_me_pipe_q(adev, 0, 0, 0, 0, 0);
> + }
> +
> amdgpu_bo_unreserve(q->mqd_obj);
> }
>
> @@ -993,9 +1005,13 @@ int amdgpu_mes_add_ring(struct amdgpu_device *adev, int gang_id,
> switch (queue_type) {
> case AMDGPU_RING_TYPE_GFX:
> ring->funcs = adev->gfx.gfx_ring[0].funcs;
> + ring->me = adev->gfx.gfx_ring[0].me;
> + ring->pipe = adev->gfx.gfx_ring[0].pipe;
> break;
> case AMDGPU_RING_TYPE_COMPUTE:
> ring->funcs = adev->gfx.compute_ring[0].funcs;
> + ring->me = adev->gfx.compute_ring[0].me;
> + ring->pipe = adev->gfx.compute_ring[0].pipe;
> break;
> case AMDGPU_RING_TYPE_SDMA:
> ring->funcs = adev->sdma.instance[0].ring.funcs;
> --
> 2.39.2
>
