[AMD Official Use Only - General]
This patch is:
Reviewed-by: Yifan Zhang <yifan1.zhang@xxxxxxx>
Best Regards,
Yifan
-----Original Message-----
From: Mahfooz, Hamza <Hamza.Mahfooz@xxxxxxx>
Sent: Friday, October 27, 2023 1:29 AM
To: amd-gfx@xxxxxxxxxxxxxxxxxxxxx
Cc: Wentland, Harry <Harry.Wentland@xxxxxxx>; Deucher, Alexander <Alexander.Deucher@xxxxxxx>; Koenig, Christian <Christian.Koenig@xxxxxxx>; Li, Sun peng (Leo) <Sunpeng.Li@xxxxxxx>; Zhang, Yifan <Yifan1.Zhang@xxxxxxx>; Siqueira, Rodrigo <Rodrigo.Siqueira@xxxxxxx>; Mahfooz, Hamza <Hamza.Mahfooz@xxxxxxx>; Broadworth, Mark <Mark.Broadworth@xxxxxxx>
Subject: [PATCH] drm/amd/display: fix S/G display enablement
An assignment statement was reversed during a refactor which effectively disabled S/G display outright. Since, we use
adev->mode_info.gpu_vm_support to indicate to the rest of the driver
that S/G display should be enabled and currently it is always set to false. So, to fix this set adev->mode_info.gpu_vm_support's value to that of init_data.flags.gpu_vm_support.
Fixes: d059c2ec6a23 ("drm/amd/display: enable S/G display for for recent APUs by default")
Reported-by: Mark Broadworth <mark.broadworth@xxxxxxx>
Tested-by: Mark Broadworth <mark.broadworth@xxxxxxx>
Signed-off-by: Hamza Mahfooz <hamza.mahfooz@xxxxxxx>
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 781d04eda3d4..adbeb2c897b5 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -1641,7 +1641,7 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
init_data.flags.gpu_vm_support = (amdgpu_sg_display != 0) && (adev->flags & AMD_IS_APU);
}
- init_data.flags.gpu_vm_support = adev->mode_info.gpu_vm_support;
+ adev->mode_info.gpu_vm_support = init_data.flags.gpu_vm_support;
if (amdgpu_dc_feature_mask & DC_FBC_MASK)
init_data.flags.fbc_support = true;
--
2.42.0
