Re: [PATCH] drm/amd check num of link levels when update pcie param

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Acked-by: Jingwen Chen <Jingwen.Chen2@xxxxxxx>

Best Regards,
JingWen Chen

On 2023/10/19 17:46, Lin.Cao wrote:
In SR-IOV environment, the value of pcie_table->num_of_link_levels will
be 0, and num_of_levels - 1 will cause array index out of bounds

Signed-off-by: Lin.Cao <lincao12@xxxxxxx>
---
  drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c | 3 +++
  1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
index bcb7ab9d2221..6906b0a7d1d1 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
@@ -2437,6 +2437,9 @@ int smu_v13_0_update_pcie_parameters(struct smu_context *smu,
  	uint32_t smu_pcie_arg;
  	int ret, i;
+ if (!num_of_levels)
+		return 0;
+
  	if (!amdgpu_device_pcie_dynamic_switching_supported()) {
  		if (pcie_table->pcie_gen[num_of_levels - 1] < pcie_gen_cap)
  			pcie_gen_cap = pcie_table->pcie_gen[num_of_levels - 1];



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