On Wed, Oct 18, 2023 at 6:17 AM Li Ma <li.ma@xxxxxxx> wrote:
>
> add get_clockgating_state, update_medium_grain_light_sleep and
> update_medium_grain_clock_gating in nbio_v7_11_funcs
> v1:
> add missing funcs in nbio_v7_11.c
> v2:
> modify the if condition and add spport for nbio v7.11 clockgating.
>
> Signed-off-by: Li Ma <li.ma@xxxxxxx>
> Reviewed-by: Yifan Zhang <yifan1.zhang@xxxxxxx>
Acked-by: Alex Deucher <alexander.deucher@xxxxxxx>
> ---
> drivers/gpu/drm/amd/amdgpu/nbio_v7_11.c | 78 +++++++++++++++++++
> drivers/gpu/drm/amd/amdgpu/soc21.c | 1 +
> .../asic_reg/nbio/nbio_7_11_0_offset.h | 6 ++
> .../asic_reg/nbio/nbio_7_11_0_sh_mask.h | 13 +++-
> 4 files changed, 97 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_11.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_11.c
> index 3a94f249929e..676ab1d20d2f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_11.c
> +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_11.c
> @@ -272,6 +272,81 @@ static void nbio_v7_11_init_registers(struct amdgpu_device *adev)
> */
> }
>
> +static void nbio_v7_11_update_medium_grain_clock_gating(struct amdgpu_device *adev,
> + bool enable)
> +{
> + uint32_t def, data;
> +
> + if (!(adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG))
> + return;
> +
> + def = data = RREG32_SOC15(NBIO, 0, regBIF_BIF256_CI256_RC3X4_USB4_CPM_CONTROL);
> + if (enable) {
> + data |= (BIF_BIF256_CI256_RC3X4_USB4_CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK |
> + BIF_BIF256_CI256_RC3X4_USB4_CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK |
> + BIF_BIF256_CI256_RC3X4_USB4_CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK |
> + BIF_BIF256_CI256_RC3X4_USB4_CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK |
> + BIF_BIF256_CI256_RC3X4_USB4_CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK |
> + BIF_BIF256_CI256_RC3X4_USB4_CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK);
> + } else {
> + data &= ~(BIF_BIF256_CI256_RC3X4_USB4_CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK |
> + BIF_BIF256_CI256_RC3X4_USB4_CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK |
> + BIF_BIF256_CI256_RC3X4_USB4_CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK |
> + BIF_BIF256_CI256_RC3X4_USB4_CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK |
> + BIF_BIF256_CI256_RC3X4_USB4_CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK |
> + BIF_BIF256_CI256_RC3X4_USB4_CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK);
> + }
> +
> + if (def != data)
> + WREG32_SOC15(NBIO, 0, regBIF_BIF256_CI256_RC3X4_USB4_CPM_CONTROL, data);
> +}
> +
> +static void nbio_v7_11_update_medium_grain_light_sleep(struct amdgpu_device *adev,
> + bool enable)
> +{
> + uint32_t def, data;
> +
> + if (!(adev->cg_flags & AMD_CG_SUPPORT_BIF_LS))
> + return;
> +
> + def = data = RREG32_SOC15(NBIO, 0, regBIF_BIF256_CI256_RC3X4_USB4_PCIE_CNTL2);
> + if (enable)
> + data |= BIF_BIF256_CI256_RC3X4_USB4_PCIE_CNTL2__SLV_MEM_LS_EN_MASK;
> + else
> + data &= ~BIF_BIF256_CI256_RC3X4_USB4_PCIE_CNTL2__SLV_MEM_LS_EN_MASK;
> +
> + if (def != data)
> + WREG32_SOC15(NBIO, 0, regBIF_BIF256_CI256_RC3X4_USB4_PCIE_CNTL2, data);
> +
> + def = data = RREG32_SOC15(NBIO, 0, regBIF_BIF256_CI256_RC3X4_USB4_PCIE_TX_POWER_CTRL_1);
> + if (enable) {
> + data |= (BIF_BIF256_CI256_RC3X4_USB4_PCIE_TX_POWER_CTRL_1__MST_MEM_LS_EN_MASK |
> + BIF_BIF256_CI256_RC3X4_USB4_PCIE_TX_POWER_CTRL_1__REPLAY_MEM_LS_EN_MASK);
> + } else {
> + data &= ~(BIF_BIF256_CI256_RC3X4_USB4_PCIE_TX_POWER_CTRL_1__MST_MEM_LS_EN_MASK |
> + BIF_BIF256_CI256_RC3X4_USB4_PCIE_TX_POWER_CTRL_1__REPLAY_MEM_LS_EN_MASK);
> + }
> +
> + if (def != data)
> + WREG32_SOC15(NBIO, 0, regBIF_BIF256_CI256_RC3X4_USB4_PCIE_TX_POWER_CTRL_1, data);
> +}
> +
> +static void nbio_v7_11_get_clockgating_state(struct amdgpu_device *adev,
> + u64 *flags)
> +{
> + uint32_t data;
> +
> + /* AMD_CG_SUPPORT_BIF_MGCG */
> + data = RREG32_SOC15(NBIO, 0, regBIF_BIF256_CI256_RC3X4_USB4_CPM_CONTROL);
> + if (data & BIF_BIF256_CI256_RC3X4_USB4_CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK)
> + *flags |= AMD_CG_SUPPORT_BIF_MGCG;
> +
> + /* AMD_CG_SUPPORT_BIF_LS */
> + data = RREG32_SOC15(NBIO, 0, regBIF_BIF256_CI256_RC3X4_USB4_PCIE_CNTL2);
> + if (data & BIF_BIF256_CI256_RC3X4_USB4_PCIE_CNTL2__SLV_MEM_LS_EN_MASK)
> + *flags |= AMD_CG_SUPPORT_BIF_LS;
> +}
> +
> const struct amdgpu_nbio_funcs nbio_v7_11_funcs = {
> .get_hdp_flush_req_offset = nbio_v7_11_get_hdp_flush_req_offset,
> .get_hdp_flush_done_offset = nbio_v7_11_get_hdp_flush_done_offset,
> @@ -288,6 +363,9 @@ const struct amdgpu_nbio_funcs nbio_v7_11_funcs = {
> .enable_doorbell_aperture = nbio_v7_11_enable_doorbell_aperture,
> .enable_doorbell_selfring_aperture = nbio_v7_11_enable_doorbell_selfring_aperture,
> .ih_doorbell_range = nbio_v7_11_ih_doorbell_range,
> + .update_medium_grain_clock_gating = nbio_v7_11_update_medium_grain_clock_gating,
> + .update_medium_grain_light_sleep = nbio_v7_11_update_medium_grain_light_sleep,
> + .get_clockgating_state = nbio_v7_11_get_clockgating_state,
> .ih_control = nbio_v7_11_ih_control,
> .init_registers = nbio_v7_11_init_registers,
> .remap_hdp_registers = nbio_v7_11_remap_hdp_registers,
> diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c b/drivers/gpu/drm/amd/amdgpu/soc21.c
> index df7462cec6ab..7fe199560264 100644
> --- a/drivers/gpu/drm/amd/amdgpu/soc21.c
> +++ b/drivers/gpu/drm/amd/amdgpu/soc21.c
> @@ -863,6 +863,7 @@ static int soc21_common_set_clockgating_state(void *handle,
> case IP_VERSION(4, 3, 0):
> case IP_VERSION(4, 3, 1):
> case IP_VERSION(7, 7, 0):
> + case IP_VERSION(7, 11, 0):
> adev->nbio.funcs->update_medium_grain_clock_gating(adev,
> state == AMD_CG_STATE_GATE);
> adev->nbio.funcs->update_medium_grain_light_sleep(adev,
> diff --git a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_11_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_11_0_offset.h
> index 846a8cf3926a..ff30f04be591 100644
> --- a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_11_0_offset.h
> +++ b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_11_0_offset.h
> @@ -775,6 +775,12 @@
> #define regPCIE_USB4_ERR_CNTL5_BASE_IDX 5
> #define regPCIE_USB4_LC_CNTL1 0x420179
> #define regPCIE_USB4_LC_CNTL1_BASE_IDX 5
> +#define regBIF_BIF256_CI256_RC3X4_USB4_CPM_CONTROL 0x420118
> +#define regBIF_BIF256_CI256_RC3X4_USB4_CPM_CONTROL_BASE_IDX 5
> +#define regBIF_BIF256_CI256_RC3X4_USB4_PCIE_CNTL2 0x42001c
> +#define regBIF_BIF256_CI256_RC3X4_USB4_PCIE_CNTL2_BASE_IDX 5
> +#define regBIF_BIF256_CI256_RC3X4_USB4_PCIE_TX_POWER_CTRL_1 0x420187
> +#define regBIF_BIF256_CI256_RC3X4_USB4_PCIE_TX_POWER_CTRL_1_BASE_IDX 5
>
>
> // addressBlock: nbio_nbif0_bif_cfg_dev0_rc_bifcfgdecp
> diff --git a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_11_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_11_0_sh_mask.h
> index 84242240f611..7f131999a263 100644
> --- a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_11_0_sh_mask.h
> +++ b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_11_0_sh_mask.h
> @@ -24634,7 +24634,18 @@
> //PCIE_USB4_LC_CNTL1
> #define PCIE_USB4_LC_CNTL1__PCIE_USB_ROUTER_CLEAR_PATH_MODE__SHIFT 0x0
> #define PCIE_USB4_LC_CNTL1__PCIE_USB_ROUTER_CLEAR_PATH_MODE_MASK 0x00000001L
> -
> +//BIF_BIF256_CI256_RC3X4_USB4_CPM_CONTROL
> +#define BIF_BIF256_CI256_RC3X4_USB4_CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK 0x00000001L
> +#define BIF_BIF256_CI256_RC3X4_USB4_CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK 0x00000002L
> +#define BIF_BIF256_CI256_RC3X4_USB4_CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK 0x00000020L
> +#define BIF_BIF256_CI256_RC3X4_USB4_CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK 0x00000040L
> +#define BIF_BIF256_CI256_RC3X4_USB4_CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK 0x00000080L
> +#define BIF_BIF256_CI256_RC3X4_USB4_CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK 0x00000100L
> +//BIF_BIF256_CI256_RC3X4_USB4_PCIE_CNTL2
> +#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_CNTL2__SLV_MEM_LS_EN_MASK 0x00010000L
> +//BIF_BIF256_CI256_RC3X4_USB4_PCIE_TX_POWER_CTRL_1
> +#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_TX_POWER_CTRL_1__MST_MEM_LS_EN_MASK 0x00000001L
> +#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_TX_POWER_CTRL_1__REPLAY_MEM_LS_EN_MASK 0x00000008L
>
> // addressBlock: nbio_nbif0_bif_cfg_dev0_rc_bifcfgdecp
> //BIF_CFG_DEV0_RC0_VENDOR_ID
> --
> 2.25.1
>
