On Wed, Oct 4, 2023 at 11:47 PM Zhang, Hawking <Hawking.Zhang@xxxxxxx> wrote:
>
> [AMD Official Use Only - General]
>
> Hmm... thinking about it more, will it override the profile mode/workload for 0xC8 or 0xCC SKU as well. In another words, does it mean the pmfw fix is general to all the 13_0_0 SKUs.
Yes, my understanding is that this should apply to all skus.
Alex
>
> Other than that, the patch looks good to me.
>
> Regards,
> Hawking
>
> -----Original Message-----
> From: amd-gfx <amd-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx> On Behalf Of Zhang, Hawking
> Sent: Thursday, October 5, 2023 11:32
> To: Deucher, Alexander <Alexander.Deucher@xxxxxxx>; amd-gfx@xxxxxxxxxxxxxxxxxxxxx
> Cc: Deucher, Alexander <Alexander.Deucher@xxxxxxx>; Liu, Kun <Kun.Liu2@xxxxxxx>
> Subject: RE: [PATCH] drm/amdgpu: Enable SMU 13.0.0 optimizations when ROCm is active (v2)
>
> [AMD Official Use Only - General]
>
> [AMD Official Use Only - General]
>
> Reviewed-by: Hawking Zhang <Hawking.Zhang@xxxxxxx>
>
> Regards,
> Hawking
> -----Original Message-----
> From: amd-gfx <amd-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx> On Behalf Of Alex Deucher
> Sent: Wednesday, October 4, 2023 23:34
> To: amd-gfx@xxxxxxxxxxxxxxxxxxxxx
> Cc: Deucher, Alexander <Alexander.Deucher@xxxxxxx>; Liu, Kun <Kun.Liu2@xxxxxxx>
> Subject: [PATCH] drm/amdgpu: Enable SMU 13.0.0 optimizations when ROCm is active (v2)
>
> From: Kun Liu <Kun.Liu2@xxxxxxx>
>
> When ROCm is active enable additional SMU 13.0.0 optimizations.
> This reuses the unused powersave profile on PMFW.
>
> v2: move to the swsmu code since we need both bits active in
> the workload mask.
>
> Signed-off-by: Alex Deucher <alexander.deucher@xxxxxxx>
> ---
> .../drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 17 ++++++++++++++++-
> 1 file changed, 16 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
> index 684b4e01fac2..83035fb1839a 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
> @@ -2447,6 +2447,7 @@ static int smu_v13_0_0_set_power_profile_mode(struct smu_context *smu,
> DpmActivityMonitorCoeffInt_t *activity_monitor =
> &(activity_monitor_external.DpmActivityMonitorCoeffInt);
> int workload_type, ret = 0;
> + u32 workload_mask;
>
> smu->power_profile_mode = input[size];
>
> @@ -2536,9 +2537,23 @@ static int smu_v13_0_0_set_power_profile_mode(struct smu_context *smu,
> if (workload_type < 0)
> return -EINVAL;
>
> + workload_mask = 1 << workload_type;
> +
> + /* Add optimizations for SMU13.0.0. Reuse the power saving profile */
> + if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_COMPUTE &&
> + (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 0)) &&
> + ((smu->adev->pm.fw_version == 0x004e6601) ||
> + (smu->adev->pm.fw_version >= 0x004e7300))) {
> + workload_type = smu_cmn_to_asic_specific_index(smu,
> + CMN2ASIC_MAPPING_WORKLOAD,
> + PP_SMC_POWER_PROFILE_POWERSAVING);
> + if (workload_type >= 0)
> + workload_mask |= 1 << workload_type;
> + }
> +
> return smu_cmn_send_smc_msg_with_param(smu,
> SMU_MSG_SetWorkloadMask,
> - 1 << workload_type,
> + workload_mask,
> NULL); }
>
> --
> 2.41.0
>
