[PATCH] drm/amd/display: fix some style issues

[Alex Deucher <alexander.deucher@xxxxxxx>]

Fixes a few style issues:
- Only calculate the dto_params and dp_hpo_inst when dccg is present.
- Fix indentation
- Drop empty else block

Fixes: 7f7925e25828 ("drm/amd/display: Fix MST recognizes connected displays as one")
Cc: Muhammad Ahmed <ahmed.ahmed@xxxxxxx>
Cc: Michel Dänzer <michel@xxxxxxxxxxx>
Cc: Stylon Wang <stylon.wang@xxxxxxx>
Signed-off-by: Alex Deucher <alexander.deucher@xxxxxxx>
---
 .../drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 13 ++++++-------
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c  |  3 +--
 2 files changed, 7 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index baecaaf96968..0276db0afab3 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -1175,18 +1175,17 @@ void dce110_disable_stream(struct pipe_ctx *pipe_ctx)
 
 	link_hwss->reset_stream_encoder(pipe_ctx);
 
-	if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {
+	if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx) && dccg) {
 		dto_params.otg_inst = tg->inst;
 		dto_params.timing = &pipe_ctx->stream->timing;
 		dp_hpo_inst = pipe_ctx->stream_res.hpo_dp_stream_enc->inst;
-		if (dccg) {
-			dccg->funcs->set_dtbclk_dto(dccg, &dto_params);
-			dccg->funcs->disable_symclk32_se(dccg, dp_hpo_inst);
-			dccg->funcs->set_dpstreamclk(dccg, REFCLK, tg->inst, dp_hpo_inst);
-		}
+
+		dccg->funcs->set_dtbclk_dto(dccg, &dto_params);
+		dccg->funcs->disable_symclk32_se(dccg, dp_hpo_inst);
+		dccg->funcs->set_dpstreamclk(dccg, REFCLK, tg->inst, dp_hpo_inst);
 	} else if (dccg && dccg->funcs->disable_symclk_se) {
 		dccg->funcs->disable_symclk_se(dccg, stream_enc->stream_enc_inst,
-				link_enc->transmitter - TRANSMITTER_UNIPHY_A);
+					       link_enc->transmitter - TRANSMITTER_UNIPHY_A);
 	}
 
 	if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index 19ab08f5122e..fd3f5d437c8d 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -2729,8 +2729,7 @@ void dcn20_enable_stream(struct pipe_ctx *pipe_ctx)
 		dto_params.timing = &pipe_ctx->stream->timing;
 		dto_params.ref_dtbclk_khz = dc->clk_mgr->funcs->get_dtb_ref_clk_frequency(dc->clk_mgr);
 		dccg->funcs->set_dtbclk_dto(dccg, &dto_params);
-	} else {
-		}
+	}
 	if (hws->funcs.calculate_dccg_k1_k2_values && dc->res_pool->dccg->funcs->set_pixel_rate_div) {
 		hws->funcs.calculate_dccg_k1_k2_values(pipe_ctx, &k1_div, &k2_div);
 
-- 
2.41.0