From: Duncan Ma <duncan.ma@xxxxxxx>
[Why]
Some of the stream encoder registers have register offset address 0. It
is causing no display in some scenarios due to DIG_FE was not setup
correctly and was not enabled.
[How]
Fix stream encoder register define list.
Reviewed-by: Charlene Liu <charlene.liu@xxxxxxx>
Acked-by: Qingqing Zhuo <qingqing.zhuo@xxxxxxx>
Signed-off-by: Duncan Ma <duncan.ma@xxxxxxx>
---
drivers/gpu/drm/amd/display/dc/dcn35/dcn35_resource.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_resource.c b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_resource.c
index 957f39e1381b..aa0c27e76e4e 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_resource.c
@@ -308,7 +308,7 @@ static const struct dcn31_apg_mask apg_mask = {
};
#define stream_enc_regs_init(id)\
- SE_DCN32_REG_LIST_RI(id)
+ SE_DCN35_REG_LIST_RI(id)
static struct dcn10_stream_enc_registers stream_enc_regs[5];
--
2.40.1
