From: Wenjing Liu <wenjing.liu@xxxxxxx>
[why]
build scaling param is overriding validation policy regarding small viewport
support. Even if ODM + windowed MPO is not supported. The decision has
to be made at the time of validation. When building scaling params, we might
be building an initial dc state as an input to DML validation. The initial state
is not supposed to be always valid and we rely on DML to modify the initial
dc state and determine the final validation result. This check is pre judging
validation result when building the initial dc state.
This causes an issue where we are transitioning from desktop only ODM
combine 2:1 to ODM bypass with 2 planes. In this case we are building
an initial state with with ODM 2:1 combine + 2 planes. This is indeed not
supported but DML is about to modify the state so it no longer uses ODM
combine. Before it reaches DML, dc resource already fails validation because
it checks that the initial state is not supported by our policy. This overrides
the ODM decision to validate this state with ODM combine disabled. Therefore
causes an unexpected validation failure when the secondary plane is added
on one side of the screen.
Reviewed-by: Dillon Varone <dillon.varone@xxxxxxx>
Acked-by: Stylon Wang <stylon.wang@xxxxxxx>
Signed-off-by: Wenjing Liu <wenjing.liu@xxxxxxx>
---
drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 7 -------
1 file changed, 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index c929003825f4..494efbede0b2 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -1371,13 +1371,6 @@ bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx)
/* depends on scaling ratios and recout, does not calculate offset yet */
calculate_viewport_size(pipe_ctx);
- if (!pipe_ctx->stream->ctx->dc->config.enable_windowed_mpo_odm) {
- /* Stopgap for validation of ODM + MPO on one side of screen case */
- if (pipe_ctx->plane_res.scl_data.viewport.height < 1 ||
- pipe_ctx->plane_res.scl_data.viewport.width < 1)
- return false;
- }
-
/*
* LB calculations depend on vp size, h/v_active and scaling ratios
* Setting line buffer pixel depth to 24bpp yields banding
--
2.42.0
