During jpeg init, CPU writes to frame buffer which can be cached by HDP,
occasionally causing invalid header to be sent to MMSCH. Perform HDP flush
after writing to frame buffer before continuing with jpeg init sequence.
Signed-off-by: Timmy Tsai <timmtsai@xxxxxxx>
---
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c
index 3eb3dcd56..27efba2da 100644
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c
@@ -33,6 +33,7 @@
#include "vcn/vcn_4_0_0_offset.h"
#include "vcn/vcn_4_0_0_sh_mask.h"
#include "ivsrcid/vcn/irqsrcs_vcn_4_0.h"
+#include "nbio/nbio_4_3_0_offset.h"
#define regUVD_JPEG_PITCH_INTERNAL_OFFSET 0x401f
@@ -468,6 +469,15 @@ static int jpeg_v4_0_start_sriov(struct amdgpu_device *adev)
table_loc = (uint32_t *)table->cpu_addr;
memcpy((void *)table_loc, &header, size);
+ /* Perform HDP flush before writing to MMSCH registers */
+ WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_GPU_HDP_FLUSH_DONE, 0x0);
+ WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_GPU_HDP_FLUSH_REQ, 0xFFF);
+ if (SOC15_WAIT_ON_RREG(NBIO, 0,
+ regBIF_BX_PF0_GPU_HDP_FLUSH_DONE, 0xFFF,
+ 0xFFF)) {
+ DRM_ERROR("Failed to flush HDP during jpeg init\n");
+ }
+
/* message MMSCH (in VCN[0]) to initialize this client
* 1, write to mmsch_vf_ctx_addr_lo/hi register with GPU mc addr
* of memory descriptor location
--
2.34.1
