From: Bas Nieuwenhuizen <bas@xxxxxxxxxxxxxxxxxxx>
This changes all BO usages in a submit to BOOKKEEP instead of READ,
which effectively disables implicit sync for these submits.
This is configured at a context level using the existing IOCTL.
Signed-off-by: Bas Nieuwenhuizen <bas@xxxxxxxxxxxxxxxxxxx>
Co-developed-by: Tatsuyuki Ishi <ishitatsuyuki@xxxxxxxxx>
Signed-off-by: Tatsuyuki Ishi <ishitatsuyuki@xxxxxxxxx>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 16 +++++++++----
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 30 +++++++++++++++++++++++++
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h | 1 +
include/uapi/drm/amdgpu_drm.h | 4 ++++
4 files changed, 47 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index 2cb814de0149..008547f97fd1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -1200,8 +1200,11 @@ static int amdgpu_cs_sync_rings(struct amdgpu_cs_parser *p)
struct dma_resv *resv = bo->tbo.base.resv;
enum amdgpu_sync_mode sync_mode;
- sync_mode = amdgpu_bo_explicit_sync(bo) ?
- AMDGPU_SYNC_EXPLICIT : AMDGPU_SYNC_NE_OWNER;
+ if (amdgpu_bo_explicit_sync(bo) || p->ctx->disable_implicit_sync)
+ sync_mode = AMDGPU_SYNC_EXPLICIT;
+ else
+ sync_mode = AMDGPU_SYNC_NE_OWNER;
+
r = amdgpu_sync_resv(p->adev, &p->sync, resv, sync_mode,
AMDGPU_SYNC_EXPLICIT, &fpriv->vm);
if (r)
@@ -1322,11 +1325,16 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p,
dma_resv_add_fence(gobj->resv,
&p->jobs[i]->base.s_fence->finished,
- DMA_RESV_USAGE_READ);
+ p->ctx->disable_implicit_sync ?
+ DMA_RESV_USAGE_BOOKKEEP :
+ DMA_RESV_USAGE_READ);
}
/* The gang leader as remembered as writer */
- dma_resv_add_fence(gobj->resv, p->fence, DMA_RESV_USAGE_WRITE);
+ dma_resv_add_fence(gobj->resv, p->fence,
+ p->ctx->disable_implicit_sync ?
+ DMA_RESV_USAGE_BOOKKEEP :
+ DMA_RESV_USAGE_WRITE);
}
seq = amdgpu_ctx_add_fence(p->ctx, p->entities[p->gang_leader_idx],
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
index 0dc9c655c4fb..fe6f30d8fd70 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
@@ -661,6 +661,30 @@ static int amdgpu_ctx_stable_pstate(struct amdgpu_device *adev,
return r;
}
+static int amdgpu_ctx_set_implicit_sync(struct amdgpu_device *adev,
+ struct amdgpu_fpriv *fpriv, uint32_t id,
+ bool enable)
+{
+ struct amdgpu_ctx *ctx;
+ struct amdgpu_ctx_mgr *mgr;
+
+ if (!fpriv)
+ return -EINVAL;
+
+ mgr = &fpriv->ctx_mgr;
+ mutex_lock(&mgr->lock);
+ ctx = idr_find(&mgr->ctx_handles, id);
+ if (!ctx) {
+ mutex_unlock(&mgr->lock);
+ return -EINVAL;
+ }
+
+ ctx->disable_implicit_sync = !enable;
+
+ mutex_unlock(&mgr->lock);
+ return 0;
+}
+
int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
struct drm_file *filp)
{
@@ -709,6 +733,12 @@ int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
return -EINVAL;
r = amdgpu_ctx_stable_pstate(adev, fpriv, id, true, &stable_pstate);
break;
+ case AMDGPU_CTX_OP_SET_IMPLICIT_SYNC:
+ if ((args->in.flags & ~AMDGPU_CTX_IMPLICIT_SYNC_ENABLED) || args->in.priority)
+ return -EINVAL;
+ r = amdgpu_ctx_set_implicit_sync(adev, fpriv, id,
+ args->in.flags & ~AMDGPU_CTX_IMPLICIT_SYNC_ENABLED);
+ break;
default:
return -EINVAL;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h
index 85376baaa92f..a330e5b65d30 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h
@@ -58,6 +58,7 @@ struct amdgpu_ctx {
unsigned long ras_counter_ue;
uint32_t stable_pstate;
struct amdgpu_ctx_mgr *ctx_mgr;
+ bool disable_implicit_sync;
};
struct amdgpu_ctx_mgr {
diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
index 79b14828d542..6a0168436c31 100644
--- a/include/uapi/drm/amdgpu_drm.h
+++ b/include/uapi/drm/amdgpu_drm.h
@@ -226,6 +226,7 @@ union drm_amdgpu_bo_list {
#define AMDGPU_CTX_OP_QUERY_STATE2 4
#define AMDGPU_CTX_OP_GET_STABLE_PSTATE 5
#define AMDGPU_CTX_OP_SET_STABLE_PSTATE 6
+#define AMDGPU_CTX_OP_SET_IMPLICIT_SYNC 7
/* GPU reset status */
#define AMDGPU_CTX_NO_RESET 0
@@ -268,6 +269,9 @@ union drm_amdgpu_bo_list {
#define AMDGPU_CTX_STABLE_PSTATE_MIN_MCLK 3
#define AMDGPU_CTX_STABLE_PSTATE_PEAK 4
+/* opt-out of implicit sync */
+#define AMDGPU_CTX_IMPLICIT_SYNC_ENABLED 1
+
struct drm_amdgpu_ctx_in {
/** AMDGPU_CTX_OP_* */
__u32 op;
--
2.41.0
