[Public]
Reviewed-by: Guchun Chen <guchun.chen@xxxxxxx>
Regards,
Guchun
> -----Original Message-----
> From: amd-gfx <amd-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx> On Behalf Of
> Srinivasan Shanmugam
> Sent: Thursday, July 27, 2023 10:37 PM
> To: Koenig, Christian <Christian.Koenig@xxxxxxx>; Deucher, Alexander
> <Alexander.Deucher@xxxxxxx>
> Cc: SHANMUGAM, SRINIVASAN <SRINIVASAN.SHANMUGAM@xxxxxxx>;
> amd-gfx@xxxxxxxxxxxxxxxxxxxxx
> Subject: [PATCH] drm/amdgpu: Clean up style problems in mmhub_v2_3.c
>
> Fixes the following:
>
> ERROR: code indent should use tabs where possible
> WARNING: Missing a blank line after declarations
> WARNING: Prefer 'unsigned int' to bare use of 'unsigned'
> WARNING: suspect code indent for conditional statements (8, 24)
> + if (!(data & (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
> [...]
> + *flags |= AMD_CG_SUPPORT_MC_MGCG;
>
> Cc: Christian König <christian.koenig@xxxxxxx>
> Cc: Alex Deucher <alexander.deucher@xxxxxxx>
> Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@xxxxxxx>
> ---
> drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c | 25 +++++++++++++----------
> --
> 1 file changed, 13 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c
> b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c
> index 8bd0fc8d9d25..1dce053a4c4d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c
> +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c
> @@ -331,7 +331,7 @@ static void mmhub_v2_3_setup_vmid_config(struct
> amdgpu_device *adev) static void
> mmhub_v2_3_program_invalidation(struct amdgpu_device *adev) {
> struct amdgpu_vmhub *hub = &adev-
> >vmhub[AMDGPU_MMHUB0(0)];
> - unsigned i;
> + unsigned int i;
>
> for (i = 0; i < 18; ++i) {
> WREG32_SOC15_OFFSET(MMHUB, 0,
> @@ -406,6 +406,7 @@ static void
> mmhub_v2_3_set_fault_enable_default(struct amdgpu_device *adev,
> bool value)
> {
> u32 tmp;
> +
> tmp = RREG32_SOC15(MMHUB, 0,
> mmMMVM_L2_PROTECTION_FAULT_CNTL);
> tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
> RANGE_PROTECTION_FAULT_ENABLE_DEFAULT,
> value); @@ -499,11 +500,11 @@
> mmhub_v2_3_update_medium_grain_clock_gating(struct amdgpu_device
> *adev,
> if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) {
> data &=
> ~MM_ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK;
> data1 &=
> ~(DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
> - DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
> - DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
> - DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
> - DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
> - DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
> + DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK
> |
> + DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK
> |
> + DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
> + DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK
> |
> + DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
>
> } else {
> data |=
> MM_ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK;
> @@ -593,13 +594,13 @@ static void mmhub_v2_3_get_clockgating(struct
> amdgpu_device *adev, u64 *flags)
>
> /* AMD_CG_SUPPORT_MC_MGCG */
> if (!(data & (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
> - DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
> - DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
> - DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
> - DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
> - DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK))
> + DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
> + DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
> + DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
> + DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
> + DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK))
> && !(data1 &
> MM_ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK)) {
> - *flags |= AMD_CG_SUPPORT_MC_MGCG;
> + *flags |= AMD_CG_SUPPORT_MC_MGCG;
> }
>
> /* AMD_CG_SUPPORT_MC_LS */
> --
> 2.25.1
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