[AMD Official Use Only - General]
Reviewed-by: Evan Quan <evan.quan@xxxxxxx>
> -----Original Message-----
> From: Kenneth Feng <kenneth.feng@xxxxxxx>
> Sent: Thursday, July 27, 2023 7:41 PM
> To: amd-gfx@xxxxxxxxxxxxxxxxxxxxx
> Cc: Quan, Evan <Evan.Quan@xxxxxxx>; Feng, Kenneth
> <Kenneth.Feng@xxxxxxx>
> Subject: [PATCH] drm/amd/pm: correct the pcie width for smu 13.0.0
>
> correct the pcie width value in pp_dpm_pcie for smu 13.0.0
>
> Signed-off-by: Kenneth Feng <kenneth.feng@xxxxxxx>
> ---
> drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
> b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
> index 232274423f9e..4bdbd3910e1f 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
> @@ -1140,7 +1140,6 @@ static int smu_v13_0_0_print_clk_levels(struct
> smu_context *smu,
> (OverDriveTableExternal_t *)smu-
> >smu_table.overdrive_table;
> struct smu_13_0_dpm_table *single_dpm_table;
> struct smu_13_0_pcie_table *pcie_table;
> - const int link_width[] = {0, 1, 2, 4, 8, 12, 16};
> uint32_t gen_speed, lane_width;
> int i, curr_freq, size = 0;
> int32_t min_value, max_value;
> @@ -1256,7 +1255,7 @@ static int smu_v13_0_0_print_clk_levels(struct
> smu_context *smu,
> (pcie_table->pcie_lane[i] == 6) ?
> "x16" : "",
> pcie_table->clk_freq[i],
> (gen_speed ==
> DECODE_GEN_SPEED(pcie_table->pcie_gen[i])) &&
> - (lane_width ==
> DECODE_LANE_WIDTH(link_width[pcie_table->pcie_lane[i]])) ?
> + (lane_width ==
> DECODE_LANE_WIDTH(pcie_table->pcie_lane[i])) ?
> "*" : "");
> break;
>
> --
> 2.34.1
