[AMD Official Use Only - General] The series is: Reviewed-by: Tao Zhou <tao.zhou1@xxxxxxx> > -----Original Message----- > From: Stanley.Yang <Stanley.Yang@xxxxxxx> > Sent: Friday, July 14, 2023 11:42 AM > To: amd-gfx@xxxxxxxxxxxxxxxxxxxxx; Zhang, Hawking <Hawking.Zhang@xxxxxxx>; > Zhou1, Tao <Tao.Zhou1@xxxxxxx>; Chai, Thomas <YiPeng.Chai@xxxxxxx>; Li, > Candice <Candice.Li@xxxxxxx> > Cc: Yang, Stanley <Stanley.Yang@xxxxxxx> > Subject: [PATCH Review V3 2/2] drm/amdgpu: Disable RAS by default on APU > flatform > > Disable RAS feature by default for aqua vanjaram on APU platform. > > Changed from V1: > Splite Disable RAS by default on APU platform into a > separated patch. > > Changed from V2: > Avoid to modify global variable amdgpu_ras_enable. > > Signed-off-by: Stanley.Yang <Stanley.Yang@xxxxxxx> > Reviewed-by: Hawking Zhang <Hawking.Zhang@xxxxxxx> > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 13 +++++++++++-- > 1 file changed, 11 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c > b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c > index 8673d9790bb0..c46e0ed9165e 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c > @@ -2524,8 +2524,17 @@ static void amdgpu_ras_check_supported(struct > amdgpu_device *adev) > /* hw_supported needs to be aligned with RAS block mask. */ > adev->ras_hw_enabled &= AMDGPU_RAS_BLOCK_MASK; > > - adev->ras_enabled = amdgpu_ras_enable == 0 ? 0 : > - adev->ras_hw_enabled & amdgpu_ras_mask; > + > + /* > + * Disable ras feature for aqua vanjaram > + * by default on apu platform. > + */ > + if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 6)) > + adev->ras_enabled = amdgpu_ras_enable != 1 ? 0 : > + adev->ras_hw_enabled & amdgpu_ras_mask; > + else > + adev->ras_enabled = amdgpu_ras_enable == 0 ? 0 : > + adev->ras_hw_enabled & amdgpu_ras_mask; > } > > static void amdgpu_ras_counte_dw(struct work_struct *work) > -- > 2.25.1
