RE: [PATCH] drm/amdgpu: Clear VCN cache when hw_init

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[AMD Official Use Only - General]

Reviewed-by: Emily Deng <Emily.Deng@xxxxxxx>

>-----Original Message-----
>From: amd-gfx <amd-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx> On Behalf Of Horace
>Chen
>Sent: Tuesday, June 20, 2023 9:30 PM
>To: amd-gfx@xxxxxxxxxxxxxxxxxxxxx
>Cc: Andrey Grodzovsky <Andrey.Grodzovsky@xxxxxxx>; Xiao, Jack
><Jack.Xiao@xxxxxxx>; Xu, Feifei <Feifei.Xu@xxxxxxx>; Chen, Horace
><Horace.Chen@xxxxxxx>; Chang, HaiJun <HaiJun.Chang@xxxxxxx>;
>Deucher, Alexander <Alexander.Deucher@xxxxxxx>; Quan, Evan
><Evan.Quan@xxxxxxx>; Koenig, Christian <Christian.Koenig@xxxxxxx>; Liu,
>Monk <Monk.Liu@xxxxxxx>; Zhang, Hawking <Hawking.Zhang@xxxxxxx>
>Subject: [PATCH] drm/amdgpu: Clear VCN cache when hw_init
>
>[Why]
>VCN will use some framebuffer space as its cache. It needs to be reset when
>reset happens, such as FLR. Otherwise some error may be kept after the reset.
>
>Signed-off-by: Horace Chen <horace.chen@xxxxxxx>
>---
> drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 3 +++
> 1 file changed, 3 insertions(+)
>
>diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
>b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
>index b48bb5212488..2db73a964031 100644
>--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
>+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
>@@ -1292,6 +1292,7 @@ static int vcn_v4_0_start_sriov(struct
>amdgpu_device *adev)
>                       cache_size);
>
>               cache_addr = adev->vcn.inst[i].gpu_addr + offset;
>+              memset(adev->vcn.inst[i].cpu_addr + offset, 0,
>+AMDGPU_VCN_STACK_SIZE);
>
>       MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
>                       regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
>                       lower_32_bits(cache_addr));
>@@ -1307,6 +1308,8 @@ static int vcn_v4_0_start_sriov(struct
>amdgpu_device *adev)
>
>               cache_addr = adev->vcn.inst[i].gpu_addr + offset +
>                       AMDGPU_VCN_STACK_SIZE;
>+              memset(adev->vcn.inst[i].cpu_addr + offset +
>AMDGPU_VCN_STACK_SIZE, 0,
>+                      AMDGPU_VCN_STACK_SIZE);
>
>       MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
>                       regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
>                       lower_32_bits(cache_addr));
>--
>2.34.1





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