RE: [PATCH v2 2/3] drm/amdgpu: Use PSP FW API for partition switch

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Reviewed-by: Hawking Zhang <Hawking.Zhang@xxxxxxx>

Regards
Hawking
-----Original Message-----
From: amd-gfx <amd-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx> On Behalf Of Lijo Lazar
Sent: Tuesday, June 13, 2023 19:03
To: amd-gfx@xxxxxxxxxxxxxxxxxxxxx
Cc: Deucher, Alexander <Alexander.Deucher@xxxxxxx>; Ma, Le <Le.Ma@xxxxxxx>; Kamal, Asad <Asad.Kamal@xxxxxxx>; Zhang, Hawking <Hawking.Zhang@xxxxxxx>
Subject: [PATCH v2 2/3] drm/amdgpu: Use PSP FW API for partition switch

Use PSP firmware interface for switching compute partitions.

Signed-off-by: Lijo Lazar <lijo.lazar@xxxxxxx>
---
v2:
        Changed the return value to int

 .../drm/amd/amdgpu/aqua_vanjaram_reg_init.c    |  3 ---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c        | 18 ++++++------------
 2 files changed, 6 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram_reg_init.c b/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram_reg_init.c
index a595bb958215..16471b81a1f5 100644
--- a/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram_reg_init.c
+++ b/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram_reg_init.c
@@ -518,9 +518,6 @@ static int aqua_vanjaram_switch_partition_mode(struct amdgpu_xcp_mgr *xcp_mgr,
                adev->gfx.funcs->switch_partition_mode(xcp_mgr->adev,
                                                       num_xcc_per_xcp);

-       if (adev->nbio.funcs->set_compute_partition_mode)
-               adev->nbio.funcs->set_compute_partition_mode(adev, mode);
-
        /* Init info about new xcps */
        *num_xcps = num_xcc / num_xcc_per_xcp;
        amdgpu_xcp_init(xcp_mgr, *num_xcps, mode); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
index f5b8d3f388ff..c1ee54d4c3d3 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
@@ -623,22 +623,16 @@ static void gfx_v9_4_3_select_me_pipe_q(struct amdgpu_device *adev,  static int gfx_v9_4_3_switch_compute_partition(struct amdgpu_device *adev,
                                                int num_xccs_per_xcp)
 {
-       int i, num_xcc;
-       u32 tmp = 0;
-
-       num_xcc = NUM_XCC(adev->gfx.xcc_mask);
+       int ret;

-       for (i = 0; i < num_xcc; i++) {
-               tmp = REG_SET_FIELD(tmp, CP_HYP_XCP_CTL, NUM_XCC_IN_XCP,
-                                   num_xccs_per_xcp);
-               tmp = REG_SET_FIELD(tmp, CP_HYP_XCP_CTL, VIRTUAL_XCC_ID,
-                                   i % num_xccs_per_xcp);
-               WREG32_SOC15(GC, GET_INST(GC, i), regCP_HYP_XCP_CTL, tmp);
-       }
+       ret = psp_spatial_partition(&adev->psp, NUM_XCC(adev->gfx.xcc_mask) /
+                                                       num_xccs_per_xcp);
+       if (ret)
+               return ret;

        adev->gfx.num_xcc_per_xcp = num_xccs_per_xcp;

-       return 0;
+       return ret;
 }

 static int gfx_v9_4_3_ih_to_xcc_inst(struct amdgpu_device *adev, int ih_node)
--
2.25.1





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