On 5/23/23 18:14, Melissa Wen wrote:
> From: Joshua Ashton <joshua@xxxxxxxxx>
>
> Multiplier to 'gain' the plane. When PQ is decoded using the fixed func
> transfer function to the internal FP16 fb, 1.0 -> 80 nits (on AMD at
> least) When sRGB is decoded, 1.0 -> 1.0. Therefore, 1.0 multiplier = 80
> nits for SDR content. So if you want, 203 nits for SDR content, pass in
> (203.0 / 80.0).
>
> Signed-off-by: Joshua Ashton <joshua@xxxxxxxxx>
> Co-developed-by: Melissa Wen <mwen@xxxxxxxxxx>
> Signed-off-by: Melissa Wen <mwen@xxxxxxxxxx>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 6 ++++++
> drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 4 ++++
> drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 12 ++++++++++++
> .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c | 13 +++++++++++++
> 4 files changed, 35 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> index fd6c4078c53a..f0e12cca295d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> @@ -1298,6 +1298,12 @@ amdgpu_display_create_color_properties(struct amdgpu_device *adev)
> return -ENOMEM;
> adev->mode_info.plane_degamma_tf_property = prop;
>
> + prop = drm_property_create_range(adev_to_drm(adev),
> + 0, "AMD_PLANE_HDR_MULT", 0, U64_MAX);
> + if (!prop)
> + return -ENOMEM;
> + adev->mode_info.plane_hdr_mult_property = prop;
> +
> return 0;
> }
> #endif
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
> index 9d7f47fe6303..c105f51b7b6d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
> @@ -365,6 +365,10 @@ struct amdgpu_mode_info {
> * linearize content with or without LUT.
> */
> struct drm_property *plane_degamma_tf_property;
> + /**
> + * @plane_hdr_mult_property:
> + */
> + struct drm_property *plane_hdr_mult_property;
> };
>
> #define AMDGPU_MAX_BL_LEVEL 0xFF
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
> index b8e432cc8078..dadbef561606 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
> @@ -51,6 +51,7 @@
>
> #define AMDGPU_DMUB_NOTIFICATION_MAX 5
>
> +#define AMDGPU_HDR_MULT_DEFAULT (0x100000000LL)
> /*
> #include "include/amdgpu_dal_power_if.h"
> #include "amdgpu_dm_irq.h"
> @@ -732,6 +733,17 @@ struct dm_plane_state {
> * linearize.
> */
> enum drm_transfer_function degamma_tf;
> + /**
> + * @hdr_mult:
> + *
> + * Multiplier to 'gain' the plane. When PQ is decoded using the fixed
> + * func transfer function to the internal FP16 fb, 1.0 -> 80 nits (on
> + * AMD at least). When sRGB is decoded, 1.0 -> 1.0, obviously.
> + * Therefore, 1.0 multiplier = 80 nits for SDR content. So if you
> + * want, 203 nits for SDR content, pass in (203.0 / 80.0). Format is
> + * S31.32 sign-magnitude.
> + */
Good explanation.
Harry
> + __u64 hdr_mult;
> };
>
> struct dm_crtc_state {
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
> index 6b71777a525c..bbbf25dd2515 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
> @@ -1322,6 +1322,7 @@ static void dm_drm_plane_reset(struct drm_plane *plane)
>
> __drm_atomic_helper_plane_reset(plane, &amdgpu_state->base);
> amdgpu_state->degamma_tf = DRM_TRANSFER_FUNCTION_DEFAULT;
> + amdgpu_state->hdr_mult = AMDGPU_HDR_MULT_DEFAULT;
> }
>
> static struct drm_plane_state *
> @@ -1345,6 +1346,7 @@ dm_drm_plane_duplicate_state(struct drm_plane *plane)
> drm_property_blob_get(dm_plane_state->degamma_lut);
>
> dm_plane_state->degamma_tf = old_dm_plane_state->degamma_tf;
> + dm_plane_state->hdr_mult = old_dm_plane_state->hdr_mult;
>
> return &dm_plane_state->base;
> }
> @@ -1450,6 +1452,10 @@ dm_atomic_plane_attach_color_mgmt_properties(struct amdgpu_display_manager *dm,
> dm->adev->mode_info.plane_degamma_tf_property,
> DRM_TRANSFER_FUNCTION_DEFAULT);
> }
> + /* HDR MULT is always available */
> + drm_object_attach_property(&plane->base,
> + dm->adev->mode_info.plane_hdr_mult_property,
> + AMDGPU_HDR_MULT_DEFAULT);
> }
>
> static int
> @@ -1476,6 +1482,11 @@ dm_atomic_plane_set_property(struct drm_plane *plane,
> dm_plane_state->degamma_tf = val;
> dm_plane_state->base.color_mgmt_changed = 1;
> }
> + } else if (property == adev->mode_info.plane_hdr_mult_property) {
> + if (dm_plane_state->hdr_mult != val) {
> + dm_plane_state->hdr_mult = val;
> + dm_plane_state->base.color_mgmt_changed = 1;
> + }
> } else {
> drm_dbg_atomic(plane->dev,
> "[PLANE:%d:%s] unknown property [PROP:%d:%s]]\n",
> @@ -1501,6 +1512,8 @@ dm_atomic_plane_get_property(struct drm_plane *plane,
> dm_plane_state->degamma_lut->base.id : 0;
> } else if (property == adev->mode_info.plane_degamma_tf_property) {
> *val = dm_plane_state->degamma_tf;
> + } else if (property == adev->mode_info.plane_hdr_mult_property) {
> + *val = dm_plane_state->hdr_mult;
> } else {
> return -EINVAL;
> }
