On 5/11/23 03:06, Michel Dänzer wrote: > On 5/10/23 22:54, Aurabindo Pillai wrote: >> On 5/10/23 09:20, Michel Dänzer wrote: >>> On 5/9/23 23:07, Pillai, Aurabindo wrote: >>>> >>>> Sorry - the firmware in the previous message is for DCN32. For Navi2x, please use the firmware attached here. >>> >>> Same problem (contents of /sys/kernel/debug/dri/0/amdgpu_firmware_info below). >>> >>> Even if it did work with newer FW, the kernel must keep working with older FW, so in that case the new behaviour would need to be guarded by the FW version. >>> >> >> Agreed. Were you able to repro the hang on any other modes/monitors? > > Haven't tried specifically, and this is the only system I have with VRR. > > Hi Michel, I've fixed a related issue on Navi21. Could you please try the attached DMCUB along with the patches to be applied on top of amd-staging-drm-next and check if the hang/corruption is gone?
From 2cfd3ea77b32b9ecbd71dd633d525a80453be04b Mon Sep 17 00:00:00 2001
From: Aurabindo Pillai <aurabindo.pillai@xxxxxxx>
Date: Wed, 31 May 2023 14:26:19 -0400
Subject: [PATCH 3/3] drm/amd/display: Program OTG vtotal min/max selectors
unconditionally for DCN1+
Due to FPO, firmware will try to change OTG timings, which would only
latch if min/max selectors for vtotal are written by the driver.
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@xxxxxxx>
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c | 15 +++------------
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c | 6 ++++++
2 files changed, 9 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
index e1975991e075..633989fd2514 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
@@ -930,19 +930,10 @@ void optc1_set_drr(
OTG_FORCE_LOCK_ON_EVENT, 0,
OTG_SET_V_TOTAL_MIN_MASK_EN, 0,
OTG_SET_V_TOTAL_MIN_MASK, 0);
-
- // Setup manual flow control for EOF via TRIG_A
- optc->funcs->setup_manual_trigger(optc);
-
- } else {
- REG_UPDATE_4(OTG_V_TOTAL_CONTROL,
- OTG_SET_V_TOTAL_MIN_MASK, 0,
- OTG_V_TOTAL_MIN_SEL, 0,
- OTG_V_TOTAL_MAX_SEL, 0,
- OTG_FORCE_LOCK_ON_EVENT, 0);
-
- optc->funcs->set_vtotal_min_max(optc, 0, 0);
}
+
+ // Setup manual flow control for EOF via TRIG_A
+ optc->funcs->setup_manual_trigger(optc);
}
void optc1_set_vtotal_min_max(struct timing_generator *optc, int vtotal_min, int vtotal_max)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
index e0edc163d767..042ce082965f 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
@@ -455,6 +455,12 @@ void optc2_setup_manual_trigger(struct timing_generator *optc)
{
struct optc *optc1 = DCN10TG_FROM_TG(optc);
+ REG_UPDATE_4(OTG_V_TOTAL_CONTROL,
+ OTG_V_TOTAL_MIN_SEL, 1,
+ OTG_V_TOTAL_MAX_SEL, 1,
+ OTG_FORCE_LOCK_ON_EVENT, 0,
+ OTG_SET_V_TOTAL_MIN_MASK, (1 << 1)); /* TRIGA */
+
REG_SET_8(OTG_TRIGA_CNTL, 0,
OTG_TRIGA_SOURCE_SELECT, 21,
OTG_TRIGA_SOURCE_PIPE_SELECT, optc->inst,
--
2.40.1
From 77e014f9bfaeb27a1c55c557791e55be24446eac Mon Sep 17 00:00:00 2001
From: Aurabindo Pillai <aurabindo.pillai@xxxxxxx>
Date: Wed, 31 May 2023 13:29:34 -0400
Subject: [PATCH 2/3] Revert "Revert "drm/amd/display: Block optimize on
consecutive FAMS enables""
This reverts commit 019d2e5cc8050ef06f4f48fe9876a7c61a862a7e.
---
.../drm/amd/display/dc/dcn20/dcn20_hwseq.c | 3 +++
.../drm/amd/display/dc/dcn30/dcn30_hwseq.c | 22 ++++++++++++++++---
2 files changed, 22 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index b56f799f10e1..b0a13eb8318c 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -2126,6 +2126,9 @@ void dcn20_optimize_bandwidth(
dc_dmub_srv_p_state_delegate(dc,
true, context);
context->bw_ctx.bw.dcn.clk.p_state_change_support = true;
+ dc->clk_mgr->clks.fw_based_mclk_switching = true;
+ } else {
+ dc->clk_mgr->clks.fw_based_mclk_switching = false;
}
dc->clk_mgr->funcs->update_clocks(
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
index 368fd5a71680..ad4e1023b00e 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
@@ -949,9 +949,13 @@ void dcn30_set_disp_pattern_generator(const struct dc *dc,
}
void dcn30_prepare_bandwidth(struct dc *dc,
- struct dc_state *context)
+ struct dc_state *context)
{
- if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) {
+ bool p_state_change_support = context->bw_ctx.bw.dcn.clk.p_state_change_support;
+ /* Any transition into an FPO config should disable MCLK switching first to avoid
+ * driver and FW P-State synchronization issues.
+ */
+ if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching || dc->clk_mgr->clks.fw_based_mclk_switching) {
dc->optimized_required = true;
context->bw_ctx.bw.dcn.clk.p_state_change_support = false;
}
@@ -962,7 +966,19 @@ void dcn30_prepare_bandwidth(struct dc *dc,
dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, dc->clk_mgr->bw_params->clk_table.entries[dc->clk_mgr->bw_params->clk_table.num_entries - 1].memclk_mhz);
dcn20_prepare_bandwidth(dc, context);
+ /*
+ * enabled -> enabled: do not disable
+ * enabled -> disabled: disable
+ * disabled -> enabled: don't care
+ * disabled -> disabled: don't care
+ */
+ if (!context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching)
+ dc_dmub_srv_p_state_delegate(dc, false, context);
- dc_dmub_srv_p_state_delegate(dc, false, context);
+ if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching || dc->clk_mgr->clks.fw_based_mclk_switching) {
+ /* After disabling P-State, restore the original value to ensure we get the correct P-State
+ * on the next optimize. */
+ context->bw_ctx.bw.dcn.clk.p_state_change_support = p_state_change_support;
+ }
}
--
2.40.1
From 4dedb96bcf26f056e7120d08aa8e6cc3c717d436 Mon Sep 17 00:00:00 2001
From: Aurabindo Pillai <aurabindo.pillai@xxxxxxx>
Date: Wed, 31 May 2023 13:29:25 -0400
Subject: [PATCH 1/3] Revert "Revert "drm/amd/display: Do not set drr on pipe
commit""
This reverts commit 984b7d7b840a1eccbbf28906470d335e2f197b63.
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 6 ++++++
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c | 7 +++++++
2 files changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index eaf9e9ccad2a..b56f799f10e1 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -2122,6 +2122,12 @@ void dcn20_optimize_bandwidth(
if (hubbub->funcs->program_compbuf_size)
hubbub->funcs->program_compbuf_size(hubbub, context->bw_ctx.bw.dcn.compbuf_size_kb, true);
+ if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) {
+ dc_dmub_srv_p_state_delegate(dc,
+ true, context);
+ context->bw_ctx.bw.dcn.clk.p_state_change_support = true;
+ }
+
dc->clk_mgr->funcs->update_clocks(
dc->clk_mgr,
context,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
index b9753867d97b..368fd5a71680 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
@@ -951,11 +951,18 @@ void dcn30_set_disp_pattern_generator(const struct dc *dc,
void dcn30_prepare_bandwidth(struct dc *dc,
struct dc_state *context)
{
+ if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) {
+ dc->optimized_required = true;
+ context->bw_ctx.bw.dcn.clk.p_state_change_support = false;
+ }
+
if (dc->clk_mgr->dc_mode_softmax_enabled)
if (dc->clk_mgr->clks.dramclk_khz <= dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000 &&
context->bw_ctx.bw.dcn.clk.dramclk_khz > dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000)
dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, dc->clk_mgr->bw_params->clk_table.entries[dc->clk_mgr->bw_params->clk_table.num_entries - 1].memclk_mhz);
dcn20_prepare_bandwidth(dc, context);
+
+ dc_dmub_srv_p_state_delegate(dc, false, context);
}
--
2.40.1
Attachment:
sienna_cichlid_dmcub.bin
Description: Binary data
