On Wed, May 24, 2023 at 5:00 AM <jiadong.zhu@xxxxxxx> wrote:
>
> From: Jiadong Zhu <Jiadong.Zhu@xxxxxxx>
>
> It is firmware requirement to set gds_backup_addrlo and gds_backup_addrhi
> of DE meta both zero if no gds partition is allocated for the frame.
Presumably other gfx versions require something similar?
Reviewed-by: Alex Deucher <alexander.deucher@xxxxxxx>
>
> Signed-off-by: Jiadong Zhu <Jiadong.Zhu@xxxxxxx>
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 13 ++++++++-----
> 1 file changed, 8 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index cbdd9918b3e7..cbcf6126cce5 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -765,7 +765,7 @@ static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev);
> static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev,
> struct amdgpu_cu_info *cu_info);
> static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev);
> -static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume);
> +static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume, bool usegds);
> static u64 gfx_v9_0_ring_get_rptr_compute(struct amdgpu_ring *ring);
> static void gfx_v9_0_query_ras_error_count(struct amdgpu_device *adev,
> void *ras_error_status);
> @@ -5160,7 +5160,8 @@ static void gfx_v9_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
> gfx_v9_0_ring_emit_de_meta(ring,
> (!amdgpu_sriov_vf(ring->adev) &&
> flags & AMDGPU_IB_PREEMPTED) ?
> - true : false);
> + true : false,
> + job->gds_size > 0 && job->gds_base != 0);
> }
>
> amdgpu_ring_write(ring, header);
> @@ -5435,7 +5436,7 @@ static int gfx_v9_0_ring_preempt_ib(struct amdgpu_ring *ring)
> return r;
> }
>
> -static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume)
> +static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume, bool usegds)
> {
> struct amdgpu_device *adev = ring->adev;
> struct v9_de_ib_state de_payload = {0};
> @@ -5466,8 +5467,10 @@ static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume)
> PAGE_SIZE);
> }
>
> - de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);
> - de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);
> + if (usegds) {
> + de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);
> + de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);
> + }
>
> cnt = (sizeof(de_payload) >> 2) + 4 - 2;
> amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
> --
> 2.25.1
>
