On Mon, Nov 14, 2022 at 8:57 PM Jonatas Esteves <jntesteves@xxxxxxxxx> wrote:
>
> Printing the other clock types should not be conditioned on being able
> to print OD_SCLK. Some GPUs currently have limited capability of only
> printing a subset of these.
>
> Since this condition was introduced in v5.18-rc1, reading from
> `pp_od_clk_voltage` has been returning empty on the Asus ROG Strix G15
> (2021).
>
> Fixes: 79c65f3fcbb1 ("drm/amd/pm: do not expose power implementation details to amdgpu_pm.c")
Can you provide your signed-off-by? Once I get that I can apply the
patch. Thanks.
Thanks,
Alex
> ---
> drivers/gpu/drm/amd/pm/amdgpu_pm.c | 12 +++++-------
> 1 file changed, 5 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
> index 236657eece47..9d364bbc78e1 100644
> --- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
> +++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
> @@ -869,13 +869,11 @@ static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev,
> }
> if (ret == -ENOENT) {
> size = amdgpu_dpm_print_clock_levels(adev, OD_SCLK, buf);
> - if (size > 0) {
> - size += amdgpu_dpm_print_clock_levels(adev, OD_MCLK, buf + size);
> - size += amdgpu_dpm_print_clock_levels(adev, OD_VDDC_CURVE, buf + size);
> - size += amdgpu_dpm_print_clock_levels(adev, OD_VDDGFX_OFFSET, buf + size);
> - size += amdgpu_dpm_print_clock_levels(adev, OD_RANGE, buf + size);
> - size += amdgpu_dpm_print_clock_levels(adev, OD_CCLK, buf + size);
> - }
> + size += amdgpu_dpm_print_clock_levels(adev, OD_MCLK, buf + size);
> + size += amdgpu_dpm_print_clock_levels(adev, OD_VDDC_CURVE, buf + size);
> + size += amdgpu_dpm_print_clock_levels(adev, OD_VDDGFX_OFFSET, buf + size);
> + size += amdgpu_dpm_print_clock_levels(adev, OD_RANGE, buf + size);
> + size += amdgpu_dpm_print_clock_levels(adev, OD_CCLK, buf + size);
> }
>
> if (size == 0)
> --
> 2.30.2
>
