On Tue, May 16, 2023 at 2:15 PM Mario Limonciello
<mario.limonciello@xxxxxxx> wrote:
>
> On GFX11 if RLC is stopped when not in GFXOFF the system will hang.
> Prevent this case from ever happening.
>
> Tested-by: Juan Martinez <Juan.Martinez@xxxxxxx>
> Signed-off-by: Mario Limonciello <mario.limonciello@xxxxxxx>
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> index dcbdb2641086..f1f879d9ed8d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> @@ -1766,6 +1766,10 @@ static void gfx_v11_0_rlc_stop(struct amdgpu_device *adev)
> {
> u32 tmp = RREG32_SOC15(GC, 0, regRLC_CNTL);
>
> + if (!adev->gfx.gfx_off_state) {
> + dev_err(adev->dev, "GFX is not in GFXOFF\n");
> + return;
> + }
This should move up before the RREG above? Also, I think it would be
cleaner to just not mess with the RLC in S0i3. Can we just return
early in smu_disable_dpms() for the APU case? All of the DPM features
are controlled by the SMU so that function is mostly a nop of APUs
anyway.
Alex
> tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
> WREG32_SOC15(GC, 0, regRLC_CNTL, tmp);
> }
> --
> 2.34.1
>
