- Add a field in struct v11_gfx_mqd for userqueue fence address. - Assign fence gpu VA address to the userqueue mqd fence address fields. v2: Remove the mask and replace with lower_32_bits (Christian) Signed-off-by: Arunpravin Paneer Selvam <Arunpravin.PaneerSelvam@xxxxxxx> Reviewed-by: Christian König <christian.koenig@xxxxxxx> --- .../gpu/drm/amd/amdgpu/amdgpu_userqueue_gfx_v11.c | 12 ++++++++++++ drivers/gpu/drm/amd/include/v11_structs.h | 4 ++-- 2 files changed, 14 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue_gfx_v11.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue_gfx_v11.c index 274e78826334..a9d41407bab1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue_gfx_v11.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue_gfx_v11.c @@ -22,6 +22,7 @@ */ #include "amdgpu.h" #include "amdgpu_userqueue.h" +#include "amdgpu_userq_fence.h" #include "v11_structs.h" #include "amdgpu_mes.h" @@ -131,6 +132,16 @@ static void amdgpu_userq_gfx_v11_destroy_ctx_space(struct amdgpu_userq_mgr *uq_m &ctx->cpu_ptr); } +static void +amdgpu_userq_set_fence_space(struct amdgpu_userq_mgr *uq_mgr, + struct amdgpu_usermode_queue *queue) +{ + struct v11_gfx_mqd *mqd = queue->mqd.cpu_ptr; + + mqd->fenceaddress_lo = lower_32_bits(queue->fence_drv->gpu_addr); + mqd->fenceaddress_hi = upper_32_bits(queue->fence_drv->gpu_addr); +} + static void amdgpu_userq_set_ctx_space(struct amdgpu_userq_mgr *uq_mgr, struct amdgpu_usermode_queue *queue) @@ -190,6 +201,7 @@ amdgpu_userq_gfx_v11_mqd_create(struct amdgpu_userq_mgr *uq_mgr, struct amdgpu_u } amdgpu_userq_set_ctx_space(uq_mgr, queue); + amdgpu_userq_set_fence_space(uq_mgr, queue); amdgpu_bo_unreserve(mqd->obj); /* Map the queue in HW using MES ring */ diff --git a/drivers/gpu/drm/amd/include/v11_structs.h b/drivers/gpu/drm/amd/include/v11_structs.h index f8008270f813..797ce6a1e56e 100644 --- a/drivers/gpu/drm/amd/include/v11_structs.h +++ b/drivers/gpu/drm/amd/include/v11_structs.h @@ -535,8 +535,8 @@ struct v11_gfx_mqd { uint32_t reserved_507; // offset: 507 (0x1FB) uint32_t reserved_508; // offset: 508 (0x1FC) uint32_t reserved_509; // offset: 509 (0x1FD) - uint32_t reserved_510; // offset: 510 (0x1FE) - uint32_t reserved_511; // offset: 511 (0x1FF) + uint32_t fenceaddress_lo; // offset: 510 (0x1FE) + uint32_t fenceaddress_hi; // offset: 511 (0x1FF) }; struct v11_sdma_mqd { -- 2.25.1