On Thu, Apr 13, 2023 at 10:25 AM Bas Nieuwenhuizen <bas@xxxxxxxxxxxxxxxxxxx> wrote: > > This info would be used by radv to figure out when we need to > split a submission into multiple submissions. radv currently has > a limit of 192 which seems to work for most gfx submissions, but > is way too high for e.g. compute or sdma. > > Userspace is available at > https://gitlab.freedesktop.org/bnieuwenhuizen/mesa/-/commits/ib-rejection-v3 > > v3: Completely rewrote based on suggestion of making it a separate query. > > Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2498 > Signed-off-by: Bas Nieuwenhuizen <bas@xxxxxxxxxxxxxxxxxxx> Maybe a 4th patch to bump the driver version? Alex > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 9 +++++++++ > include/uapi/drm/amdgpu_drm.h | 2 ++ > 2 files changed, 11 insertions(+) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c > index 0efb38539d70..1a2e342af1c0 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c > @@ -1140,6 +1140,15 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) > kfree(caps); > return r; > } > + case AMDGPU_INFO_MAX_IBS: { > + uint32_t max_ibs[AMDGPU_HW_IP_NUM]; > + > + for (i = 0; i < AMDGPU_HW_IP_NUM; ++i) > + max_ibs[i] = amdgpu_ring_max_ibs(i); > + > + return copy_to_user(out, max_ibs, > + min((size_t)size, sizeof(max_ibs))) ? -EFAULT : 0; > + } > default: > DRM_DEBUG_KMS("Invalid request %d\n", info->query); > return -EINVAL; > diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h > index b6eb90df5d05..6981e59a9401 100644 > --- a/include/uapi/drm/amdgpu_drm.h > +++ b/include/uapi/drm/amdgpu_drm.h > @@ -876,6 +876,8 @@ struct drm_amdgpu_cs_chunk_data { > #define AMDGPU_INFO_VIDEO_CAPS_DECODE 0 > /* Subquery id: Encode */ > #define AMDGPU_INFO_VIDEO_CAPS_ENCODE 1 > +/* Query the max number of IBs per gang per submission */ > +#define AMDGPU_INFO_MAX_IBS 0x22 > > #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 > #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff > -- > 2.40.0 >
