On 2023-03-29 12:04, Shashank Sharma wrote: > From: Shashank Sharma <contactshashanksharma@xxxxxxxxx> > > This patch adds skeleton code for amdgpu usermode queue. It contains: > - A new files with init functions of usermode queues. > - A queue context manager in driver private data. > > V1: Worked on design review comments from RFC patch series: > (https://patchwork.freedesktop.org/series/112214/) > - Alex: Keep a list of queues, instead of single queue per process. > - Christian: Use the queue manager instead of global ptrs, > Don't keep the queue structure in amdgpu_ctx > > V2: > - Reformatted code, split the big patch into two > > V3: > - Integration with doorbell manager > > Cc: Alex Deucher <alexander.deucher@xxxxxxx> > Cc: Christian Koenig <christian.koenig@xxxxxxx> > Signed-off-by: Shashank Sharma <contactshashanksharma@xxxxxxxxx> > --- > drivers/gpu/drm/amd/amdgpu/Makefile | 2 + > drivers/gpu/drm/amd/amdgpu/amdgpu.h | 10 +++- > drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 1 + > drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 6 +++ > drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c | 39 +++++++++++++++ > .../gpu/drm/amd/include/amdgpu_userqueue.h | 49 +++++++++++++++++++ > 6 files changed, 106 insertions(+), 1 deletion(-) > create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c > create mode 100644 drivers/gpu/drm/amd/include/amdgpu_userqueue.h > > diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile > index 204665f20319..2d90ba618e5d 100644 > --- a/drivers/gpu/drm/amd/amdgpu/Makefile > +++ b/drivers/gpu/drm/amd/amdgpu/Makefile > @@ -210,6 +210,8 @@ amdgpu-y += \ > # add amdkfd interfaces > amdgpu-y += amdgpu_amdkfd.o > > +# add usermode queue > +amdgpu-y += amdgpu_userqueue.o > > ifneq ($(CONFIG_HSA_AMD),) > AMDKFD_PATH := ../amdkfd > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h > index 6b74df446694..c5f9af0e74ee 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h > @@ -438,6 +438,14 @@ struct amdgpu_sa_manager { > uint32_t align; > }; > > +/* Gfx usermode queues */ > +struct amdgpu_userq_mgr { > + struct idr userq_idr; > + struct mutex userq_mutex; > + struct amdgpu_device *adev; > + const struct amdgpu_userq_funcs *userq_funcs[AMDGPU_HW_IP_NUM]; > +}; > + Could you align the member names to the largest member's column, as opposed to having only a single space in between? It makes it so much more readable. > /* sub-allocation buffer */ > struct amdgpu_sa_bo { > struct list_head olist; > @@ -470,7 +478,6 @@ struct amdgpu_flip_work { > bool async; > }; > > - > /* > * file private structure > */ > @@ -482,6 +489,7 @@ struct amdgpu_fpriv { > struct mutex bo_list_lock; > struct idr bo_list_handles; > struct amdgpu_ctx_mgr ctx_mgr; > + struct amdgpu_userq_mgr userq_mgr; > }; Like here, and pretty much the rest of the kernel code. > > int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv); > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c > index b4f2d61ea0d5..2d6bcfd727c8 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c > @@ -52,6 +52,7 @@ > #include "amdgpu_ras.h" > #include "amdgpu_xgmi.h" > #include "amdgpu_reset.h" > +#include "amdgpu_userqueue.h" > > /* > * KMS wrapper. > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c > index 7aa7e52ca784..b16b8155a157 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c > @@ -43,6 +43,7 @@ > #include "amdgpu_gem.h" > #include "amdgpu_display.h" > #include "amdgpu_ras.h" > +#include "amdgpu_userqueue.h" > > void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev) > { > @@ -1187,6 +1188,10 @@ int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) > > amdgpu_ctx_mgr_init(&fpriv->ctx_mgr, adev); > > + r = amdgpu_userq_mgr_init(&fpriv->userq_mgr, adev); > + if (r) > + DRM_WARN("Can't setup usermode queues, only legacy workload submission will work\n"); > + > file_priv->driver_priv = fpriv; > goto out_suspend; > > @@ -1254,6 +1259,7 @@ void amdgpu_driver_postclose_kms(struct drm_device *dev, > > amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr); > amdgpu_vm_fini(adev, &fpriv->vm); > + amdgpu_userq_mgr_fini(&fpriv->userq_mgr); > > if (pasid) > amdgpu_pasid_free_delayed(pd->tbo.base.resv, pasid); > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c > new file mode 100644 > index 000000000000..13e1eebc1cb6 > --- /dev/null > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c > @@ -0,0 +1,39 @@ > +/* > + * Copyright 2022 Advanced Micro Devices, Inc. > + * > + * Permission is hereby granted, free of charge, to any person obtaining a > + * copy of this software and associated documentation files (the "Software"), > + * to deal in the Software without restriction, including without limitation > + * the rights to use, copy, modify, merge, publish, distribute, sublicense, > + * and/or sell copies of the Software, and to permit persons to whom the > + * Software is furnished to do so, subject to the following conditions: > + * > + * The above copyright notice and this permission notice shall be included in > + * all copies or substantial portions of the Software. > + * > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL > + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR > + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, > + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR > + * OTHER DEALINGS IN THE SOFTWARE. > + * > + */ > + > +#include "amdgpu.h" > + > +int amdgpu_userq_mgr_init(struct amdgpu_userq_mgr *userq_mgr, struct amdgpu_device *adev) > +{ > + mutex_init(&userq_mgr->userq_mutex); > + idr_init_base(&userq_mgr->userq_idr, 1); > + userq_mgr->adev = adev; > + > + return 0; > +} > + > +void amdgpu_userq_mgr_fini(struct amdgpu_userq_mgr *userq_mgr) > +{ > + idr_destroy(&userq_mgr->userq_idr); > + mutex_destroy(&userq_mgr->userq_mutex); > +} > diff --git a/drivers/gpu/drm/amd/include/amdgpu_userqueue.h b/drivers/gpu/drm/amd/include/amdgpu_userqueue.h > new file mode 100644 > index 000000000000..7eeb8c9e6575 > --- /dev/null > +++ b/drivers/gpu/drm/amd/include/amdgpu_userqueue.h > @@ -0,0 +1,49 @@ > +/* > + * Copyright 2022 Advanced Micro Devices, Inc. > + * > + * Permission is hereby granted, free of charge, to any person obtaining a > + * copy of this software and associated documentation files (the "Software"), > + * to deal in the Software without restriction, including without limitation > + * the rights to use, copy, modify, merge, publish, distribute, sublicense, > + * and/or sell copies of the Software, and to permit persons to whom the > + * Software is furnished to do so, subject to the following conditions: > + * > + * The above copyright notice and this permission notice shall be included in > + * all copies or substantial portions of the Software. > + * > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL > + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR > + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, > + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR > + * OTHER DEALINGS IN THE SOFTWARE. > + * > + */ > + > +#ifndef AMDGPU_USERQUEUE_H_ > +#define AMDGPU_USERQUEUE_H_ > + > +#include "amdgpu.h" > +#define AMDGPU_MAX_USERQ 512 > + > +struct amdgpu_usermode_queue { > + int queue_id; > + int queue_type; > + uint64_t flags; > + uint64_t doorbell_handle; > + struct amdgpu_vm *vm; > + struct amdgpu_userq_mgr *userq_mgr; > + struct amdgpu_mqd_prop userq_prop; > +}; Could you align the member names to the largest member's column, as opposed to having only a single space in between? It makes it so much more readable. > + > +struct amdgpu_userq_funcs { > + int (*mqd_create)(struct amdgpu_userq_mgr *, struct amdgpu_usermode_queue *); > + void (*mqd_destroy)(struct amdgpu_userq_mgr *, struct amdgpu_usermode_queue *); > +}; Here too, align to the largest column. Regards, Luben > + > +int amdgpu_userq_mgr_init(struct amdgpu_userq_mgr *userq_mgr, struct amdgpu_device *adev); > + > +void amdgpu_userq_mgr_fini(struct amdgpu_userq_mgr *userq_mgr); > + > +#endif
