Series is,
Acked-by: Luben Tuikov <luben.tuikov@xxxxxxx>
Regards,
Luben
On 2023-03-29 06:51, Tong Liu01 wrote:
> User can check pp_dpm_vclk1 and pp_dpm_dclk1 for DPM frequency of
> vcn and dcn
>
> Signed-off-by: Tong Liu01 <Tong.Liu01@xxxxxxx>
> ---
> .../gpu/drm/amd/include/kgd_pp_interface.h | 2 ++
> drivers/gpu/drm/amd/pm/amdgpu_pm.c | 32 +++++++++++++++++++
> drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 8 +++++
> 3 files changed, 42 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> index 86b6b0c9fb02..9f542f6e19ed 100644
> --- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> +++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> @@ -104,7 +104,9 @@ enum pp_clock_type {
> PP_FCLK,
> PP_DCEFCLK,
> PP_VCLK,
> + PP_VCLK1,
> PP_DCLK,
> + PP_DCLK1,
> OD_SCLK,
> OD_MCLK,
> OD_VDDC_CURVE,
> diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
> index d75a67cfe523..9991447b5f14 100644
> --- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
> +++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
> @@ -1180,6 +1180,21 @@ static ssize_t amdgpu_set_pp_dpm_vclk(struct device *dev,
> return amdgpu_set_pp_dpm_clock(dev, PP_VCLK, buf, count);
> }
>
> +static ssize_t amdgpu_get_pp_dpm_vclk1(struct device *dev,
> + struct device_attribute *attr,
> + char *buf)
> +{
> + return amdgpu_get_pp_dpm_clock(dev, PP_VCLK1, buf);
> +}
> +
> +static ssize_t amdgpu_set_pp_dpm_vclk1(struct device *dev,
> + struct device_attribute *attr,
> + const char *buf,
> + size_t count)
> +{
> + return amdgpu_set_pp_dpm_clock(dev, PP_VCLK1, buf, count);
> +}
> +
> static ssize_t amdgpu_get_pp_dpm_dclk(struct device *dev,
> struct device_attribute *attr,
> char *buf)
> @@ -1195,6 +1210,21 @@ static ssize_t amdgpu_set_pp_dpm_dclk(struct device *dev,
> return amdgpu_set_pp_dpm_clock(dev, PP_DCLK, buf, count);
> }
>
> +static ssize_t amdgpu_get_pp_dpm_dclk1(struct device *dev,
> + struct device_attribute *attr,
> + char *buf)
> +{
> + return amdgpu_get_pp_dpm_clock(dev, PP_DCLK, buf);
> +}
> +
> +static ssize_t amdgpu_set_pp_dpm_dclk1(struct device *dev,
> + struct device_attribute *attr,
> + const char *buf,
> + size_t count)
> +{
> + return amdgpu_set_pp_dpm_clock(dev, PP_DCLK, buf, count);
> +}
> +
> static ssize_t amdgpu_get_pp_dpm_dcefclk(struct device *dev,
> struct device_attribute *attr,
> char *buf)
> @@ -2002,7 +2032,9 @@ static struct amdgpu_device_attr amdgpu_device_attrs[] = {
> AMDGPU_DEVICE_ATTR_RW(pp_dpm_socclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
> AMDGPU_DEVICE_ATTR_RW(pp_dpm_fclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
> AMDGPU_DEVICE_ATTR_RW(pp_dpm_vclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
> + AMDGPU_DEVICE_ATTR_RW(pp_dpm_vclk1, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
> AMDGPU_DEVICE_ATTR_RW(pp_dpm_dclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
> + AMDGPU_DEVICE_ATTR_RW(pp_dpm_dclk1, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
> AMDGPU_DEVICE_ATTR_RW(pp_dpm_dcefclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
> AMDGPU_DEVICE_ATTR_RW(pp_dpm_pcie, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
> AMDGPU_DEVICE_ATTR_RW(pp_sclk_od, ATTR_FLAG_BASIC),
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> index 94fe8593444a..056ac2b512eb 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> @@ -2022,8 +2022,12 @@ static int smu_force_ppclk_levels(void *handle,
> clk_type = SMU_DCEFCLK; break;
> case PP_VCLK:
> clk_type = SMU_VCLK; break;
> + case PP_VCLK1:
> + clk_type = SMU_VCLK1; break;
> case PP_DCLK:
> clk_type = SMU_DCLK; break;
> + case PP_DCLK1:
> + clk_type = SMU_DCLK1; break;
> case OD_SCLK:
> clk_type = SMU_OD_SCLK; break;
> case OD_MCLK:
> @@ -2409,8 +2413,12 @@ static enum smu_clk_type smu_convert_to_smuclk(enum pp_clock_type type)
> clk_type = SMU_DCEFCLK; break;
> case PP_VCLK:
> clk_type = SMU_VCLK; break;
> + case PP_VCLK1:
> + clk_type = SMU_VCLK1; break;
> case PP_DCLK:
> clk_type = SMU_DCLK; break;
> + case PP_DCLK1:
> + clk_type = SMU_DCLK1; break;
> case OD_SCLK:
> clk_type = SMU_OD_SCLK; break;
> case OD_MCLK:
