[AMD Official Use Only - General]
Hi Lijo.
> -----Original Message-----
> From: Lazar, Lijo <Lijo.Lazar@xxxxxxx>
> Sent: Monday, March 27, 2023 8:34 PM
> To: Yang, WenYou <WenYou.Yang@xxxxxxx>; Deucher, Alexander
> <Alexander.Deucher@xxxxxxx>; Koenig, Christian
> <Christian.Koenig@xxxxxxx>; Pan, Xinhui <Xinhui.Pan@xxxxxxx>; Quan,
> Evan <Evan.Quan@xxxxxxx>; Limonciello, Mario
> <Mario.Limonciello@xxxxxxx>
> Cc: Yuan, Perry <Perry.Yuan@xxxxxxx>; Li, Ying <YING.LI@xxxxxxx>; amd-
> gfx@xxxxxxxxxxxxxxxxxxxxx; gpiccoli@xxxxxxxxxx; Liu, Kun
> <Kun.Liu2@xxxxxxx>; Liang, Richard qi <Richardqi.Liang@xxxxxxx>
> Subject: Re: [PATCH v2 2/3] drm/amd/pm: send the SMT enable message to
> pmfw
>
>
>
> On 3/27/2023 12:54 PM, Wenyou Yang wrote:
> > When the CPU SMT status is changed in the fly, sent the SMT enable
> > message to pmfw to notify it that the SMT status changed.
> >
> > Signed-off-by: Wenyou Yang <WenYou.Yang@xxxxxxx>
> > ---
> > drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 39
> +++++++++++++++++++
> > drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 7 ++++
> > 2 files changed, 46 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> > b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> > index b5d64749990e..eb4c49f38292 100644
> > --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> > +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> > @@ -22,6 +22,7 @@
> >
> > #define SWSMU_CODE_LAYER_L1
> >
> > +#include <linux/cpu.h>
> > #include <linux/firmware.h>
> > #include <linux/pci.h>
> >
> > @@ -54,6 +55,8 @@
> > #undef pr_info
> > #undef pr_debug
> >
> > +extern struct raw_notifier_head smt_notifier_head;
> > +
> > static const struct amd_pm_funcs swsmu_pm_funcs;
> > static int smu_force_smuclk_levels(struct smu_context *smu,
> > enum smu_clk_type clk_type,
> > @@ -69,6 +72,9 @@ static int smu_set_fan_speed_rpm(void *handle,
> uint32_t speed);
> > static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled);
> > static int smu_set_mp1_state(void *handle, enum pp_mp1_state
> > mp1_state);
> >
> > +static int smt_notifier_callback(struct notifier_block *nb,
> > + unsigned long action, void *data);
> > +
> > static int smu_sys_get_pp_feature_mask(void *handle,
> > char *buf)
> > {
> > @@ -647,6 +653,8 @@ static int smu_early_init(void *handle)
> > adev->powerplay.pp_handle = smu;
> > adev->powerplay.pp_funcs = &swsmu_pm_funcs;
> >
> > + smu->nb.notifier_call = smt_notifier_callback;
> > +
> > r = smu_set_funcs(adev);
> > if (r)
> > return r;
> > @@ -1105,6 +1113,8 @@ static int smu_sw_init(void *handle)
> > if (!smu->ppt_funcs->get_fan_control_mode)
> > smu->adev->pm.no_fan = true;
> >
> > + raw_notifier_chain_register(&smt_notifier_head, &smu->nb);
> > +
>
> As mentioned before, it's not a blind registration for any ASIC. This should
> only be done by the ASICs which are interested in the notification and not here.
> So this should be somewhere inside vangogh_set_ppt_funcs or part of a
> software init callback like vangogh_init_smc_tables.
>
> Thanks,
> Lijo
You are right, only Vangogh PMFW will handle the CCLK PD Limit update request.
Hi @Yang, WenYou
It will need to limit the update message within the Vangogh Asic.
>
> > return 0;
> > }
> >
> > @@ -1122,6 +1132,9 @@ static int smu_sw_fini(void *handle)
> >
> > smu_fini_microcode(smu);
> >
> > + if (smu->nb.notifier_call != NULL)
> > + raw_notifier_chain_unregister(&smt_notifier_head, &smu-
> >nb);
> > +
> > return 0;
> > }
> >
> > @@ -3241,3 +3254,29 @@ int smu_send_hbm_bad_channel_flag(struct
> > smu_context *smu, uint32_t size)
> >
> > return ret;
> > }
> > +
> > +static int smu_set_cpu_smt_enable(struct smu_context *smu, bool
> > +enable) {
> > + int ret = -EINVAL;
> > +
> > + if (smu->ppt_funcs && smu->ppt_funcs->set_cpu_smt_enable)
> > + ret = smu->ppt_funcs->set_cpu_smt_enable(smu, enable);
> > +
> > + return ret;
> > +}
> > +
> > +static int smt_notifier_callback(struct notifier_block *nb,
> > + unsigned long action, void *data) {
> > + struct smu_context *smu = container_of(nb, struct smu_context, nb);
> > + int ret;
> > +
> > + smu = container_of(nb, struct smu_context, nb);
> > +
> > + ret = smu_set_cpu_smt_enable(smu, action == SMT_ENABLED);
> > +
> > + dev_dbg(smu->adev->dev, "failed to set cclk_pd_limit for
> SMT %sabled: %d\n",
> > + action == SMT_ENABLED ? "en" : "dis", ret);
> > +
> > + return ret ? NOTIFY_BAD : NOTIFY_OK; }
> > diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
> > b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
> > index 09469c750a96..4d51ac5ec8ba 100644
> > --- a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
> > +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
> > @@ -566,6 +566,8 @@ struct smu_context
> >
> > struct firmware pptable_firmware;
> >
> > + struct notifier_block nb;
> > +
> > u32 param_reg;
> > u32 msg_reg;
> > u32 resp_reg;
> > @@ -1354,6 +1356,11 @@ struct pptable_funcs {
> > * @init_pptable_microcode: Prepare the pptable microcode to
> upload via PSP
> > */
> > int (*init_pptable_microcode)(struct smu_context *smu);
> > +
> > + /**
> > + * @set_cpu_smt_enable: Set the CPU SMT status.
> > + */
> > + int (*set_cpu_smt_enable)(struct smu_context *smu, bool
> smt_enable);
> > };
> >
> > typedef enum {
