[AMD Official Use Only - General] Thanks a lot Christian!, much appreciate for your help! Best Regards, Srini -----Original Message----- From: Koenig, Christian <Christian.Koenig@xxxxxxx> Sent: Thursday, March 23, 2023 6:59 PM To: SHANMUGAM, SRINIVASAN <SRINIVASAN.SHANMUGAM@xxxxxxx>; Deucher, Alexander <Alexander.Deucher@xxxxxxx>; Limonciello, Mario <Mario.Limonciello@xxxxxxx>; Zhang, Hawking <Hawking.Zhang@xxxxxxx>; Tuikov, Luben <Luben.Tuikov@xxxxxxx> Cc: amd-gfx@xxxxxxxxxxxxxxxxxxxxx Subject: Re: [PATCH] drm/amd/amdgpu: Fix logic bug in fatal error handling Am 23.03.23 um 13:04 schrieb Srinivasan Shanmugam: > CC drivers/gpu/drm/amd/amdgpu/amdgpu_ras.o > drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c:2567:28: error: bitwise or with non-zero value always evaluates to true [-Werror,-Wtautological-bitwise-compare] > if (adev->ras_hw_enabled | AMDGPU_RAS_BLOCK__DF) > ~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~ > > Presumably the author intended to test if AMDGPU_RAS_BLOCK__DF bit was > set if ras is enabled, so that's what I'm changing the code to. > Hopefully to do the right thing. That looks like a nice catch to me, but I don't really know the ras code that well. Hawking, Luben or whoever is more familiar with that should probably comment as well. Christian. > > Cc: Christian König <christian.koenig@xxxxxxx> > Cc: Alex Deucher <alexander.deucher@xxxxxxx> > Cc: Mario Limonciello <mario.limonciello@xxxxxxx> > Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@xxxxxxx> > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c > b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c > index 5b17790218811..fac45f98145d8 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c > @@ -2564,7 +2564,7 @@ int amdgpu_ras_init(struct amdgpu_device *adev) > adev->nbio.ras = &nbio_v7_4_ras; > break; > case IP_VERSION(4, 3, 0): > - if (adev->ras_hw_enabled | AMDGPU_RAS_BLOCK__DF) > + if (adev->ras_hw_enabled & AMDGPU_RAS_BLOCK__DF) > /* unlike other generation of nbio ras, > * nbio v4_3 only support fatal error interrupt > * to inform software that DF is freezed due to
