Hi, Christian, On Mon, Mar 6, 2023 at 12:40 AM Christian König <christian.koenig@xxxxxxx> wrote: > > Am 05.03.23 um 06:21 schrieb Huacai Chen: > > LoongArch maintains cache coherency in hardware, but its WUC attribute > > (Weak-ordered UnCached, which is similar to WC) is out of the scope of > > cache coherency machanism. This means WUC can only used for write-only > > memory regions. So use uncached ioremap() for LoongArch in the amdgpu > > driver. > > Well NAK. This is leaking platform dependencies into the driver code. Then is it acceptable to let ioremap() depend on drm_arch_can_wc_memory()? Huacai > > When you have a limitation that ioremap_wc() can't guarantee read/write > ordering then that's pretty clearly a platform bug and you would need to > apply this workaround to all drivers using ioremap_wc() which isn't > really feasible. > > The x86 cache dependencies is because the GPU can also be part of the > CPU in which case PCIe is not used to access the aperture base. > > Regards, > Christian. > > > > > Signed-off-by: Huacai Chen <chenhuacai@xxxxxxxxxxx> > > --- > > drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 5 +++++ > > 1 file changed, 5 insertions(+) > > > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c > > index c5ef7f7bdc15..c6888a58819a 100644 > > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c > > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c > > @@ -1750,8 +1750,13 @@ int amdgpu_ttm_init(struct amdgpu_device *adev) > > > > else > > #endif > > +#ifdef CONFIG_LOONGARCH > > + adev->mman.aper_base_kaddr = ioremap(adev->gmc.aper_base, > > + adev->gmc.visible_vram_size); > > +#else > > adev->mman.aper_base_kaddr = ioremap_wc(adev->gmc.aper_base, > > adev->gmc.visible_vram_size); > > +#endif > > #endif > > > > /* >
