Re: [PATCH 1/4] drm/amdgpu/nv: don't expose AV1 if VCN0 is harvested

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Acked-by: Christian König <christian.koenig@xxxxxxx>

Regards,
Christian.

Am 18.01.23 um 02:09 schrieb Liu, Leo:
[AMD Official Use Only - General]

The series are:

Reviewed-by: Leo Liu <leo.liu@xxxxxxx>


-----Original Message-----
From: amd-gfx <amd-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx> On Behalf Of Alex Deucher
Sent: January 17, 2023 3:00 PM
To: amd-gfx@xxxxxxxxxxxxxxxxxxxxx
Cc: Deucher, Alexander <Alexander.Deucher@xxxxxxx>
Subject: [PATCH 1/4] drm/amdgpu/nv: don't expose AV1 if VCN0 is harvested

Only VCN0 supports AV1.

Signed-off-by: Alex Deucher <alexander.deucher@xxxxxxx>
---
  drivers/gpu/drm/amd/amdgpu/nv.c | 101 +++++++++++++++++++++++++-------
  1 file changed, 81 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c index 6853b93ac82e..d972025f0d20 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -98,7 +98,7 @@ static const struct amdgpu_video_codecs nv_video_codecs_decode =  };

  /* Sienna Cichlid */
-static const struct amdgpu_video_codec_info sc_video_codecs_decode_array[] =
+static const struct amdgpu_video_codec_info
+sc_video_codecs_decode_array_vcn0[] =
  {
         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)},
         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)}, @@ -110,10 +110,27 @@ static const struct amdgpu_video_codec_info sc_video_codecs_decode_array[] =
         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},  };

-static const struct amdgpu_video_codecs sc_video_codecs_decode =
+static const struct amdgpu_video_codec_info
+sc_video_codecs_decode_array_vcn1[] =
  {
-       .codec_count = ARRAY_SIZE(sc_video_codecs_decode_array),
-       .codec_array = sc_video_codecs_decode_array,
+       {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)},
+       {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)},
+       {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
+       {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)},
+       {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
+       {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
+       {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352,
+0)}, };
+
+static const struct amdgpu_video_codecs sc_video_codecs_decode_vcn0 = {
+       .codec_count = ARRAY_SIZE(sc_video_codecs_decode_array_vcn0),
+       .codec_array = sc_video_codecs_decode_array_vcn0,
+};
+
+static const struct amdgpu_video_codecs sc_video_codecs_decode_vcn1 = {
+       .codec_count = ARRAY_SIZE(sc_video_codecs_decode_array_vcn1),
+       .codec_array = sc_video_codecs_decode_array_vcn1,
  };

  /* SRIOV Sienna Cichlid, not const since data is controlled by host */ @@ -123,7 +140,7 @@ static struct amdgpu_video_codec_info sriov_sc_video_codecs_encode_array[] =
         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)},  };

-static struct amdgpu_video_codec_info sriov_sc_video_codecs_decode_array[] =
+static struct amdgpu_video_codec_info
+sriov_sc_video_codecs_decode_array_vcn0[] =
  {
         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)},
         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)}, @@ -135,16 +152,33 @@ static struct amdgpu_video_codec_info sriov_sc_video_codecs_decode_array[] =
         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},  };

+static struct amdgpu_video_codec_info
+sriov_sc_video_codecs_decode_array_vcn1[] = {
+       {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)},
+       {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)},
+       {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
+       {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)},
+       {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
+       {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
+       {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352,
+0)}, };
+
  static struct amdgpu_video_codecs sriov_sc_video_codecs_encode =  {
         .codec_count = ARRAY_SIZE(sriov_sc_video_codecs_encode_array),
         .codec_array = sriov_sc_video_codecs_encode_array,
  };

-static struct amdgpu_video_codecs sriov_sc_video_codecs_decode =
+static struct amdgpu_video_codecs sriov_sc_video_codecs_decode_vcn0 =
  {
-       .codec_count = ARRAY_SIZE(sriov_sc_video_codecs_decode_array),
-       .codec_array = sriov_sc_video_codecs_decode_array,
+       .codec_count = ARRAY_SIZE(sriov_sc_video_codecs_decode_array_vcn0),
+       .codec_array = sriov_sc_video_codecs_decode_array_vcn0,
+};
+
+static struct amdgpu_video_codecs sriov_sc_video_codecs_decode_vcn1 = {
+       .codec_count = ARRAY_SIZE(sriov_sc_video_codecs_decode_array_vcn1),
+       .codec_array = sriov_sc_video_codecs_decode_array_vcn1,
  };

  /* Beige Goby*/
@@ -181,20 +215,37 @@ static const struct amdgpu_video_codecs yc_video_codecs_decode = {  static int nv_query_video_codecs(struct amdgpu_device *adev, bool encode,
                                  const struct amdgpu_video_codecs **codecs)  {
+       if (adev->vcn.num_vcn_inst == hweight8(adev->vcn.harvest_config))
+               return -EINVAL;
+
         switch (adev->ip_versions[UVD_HWIP][0]) {
         case IP_VERSION(3, 0, 0):
         case IP_VERSION(3, 0, 64):
         case IP_VERSION(3, 0, 192):
                 if (amdgpu_sriov_vf(adev)) {
-                       if (encode)
-                               *codecs = &sriov_sc_video_codecs_encode;
-                       else
-                               *codecs = &sriov_sc_video_codecs_decode;
+                       if (adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) {
+                               if (encode)
+                                       *codecs = &sriov_sc_video_codecs_encode;
+                               else
+                                       *codecs = &sriov_sc_video_codecs_decode_vcn1;
+                       } else {
+                               if (encode)
+                                       *codecs = &sriov_sc_video_codecs_encode;
+                               else
+                                       *codecs = &sriov_sc_video_codecs_decode_vcn0;
+                       }
                 } else {
-                       if (encode)
-                               *codecs = &nv_video_codecs_encode;
-                       else
-                               *codecs = &sc_video_codecs_decode;
+                       if (adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) {
+                               if (encode)
+                                       *codecs = &nv_video_codecs_encode;
+                               else
+                                       *codecs = &sc_video_codecs_decode_vcn1;
+                       } else {
+                               if (encode)
+                                       *codecs = &nv_video_codecs_encode;
+                               else
+                                       *codecs = &sc_video_codecs_decode_vcn0;
+                       }
                 }
                 return 0;
         case IP_VERSION(3, 0, 16):
@@ -202,7 +253,7 @@ static int nv_query_video_codecs(struct amdgpu_device *adev, bool encode,
                 if (encode)
                         *codecs = &nv_video_codecs_encode;
                 else
-                       *codecs = &sc_video_codecs_decode;
+                       *codecs = &sc_video_codecs_decode_vcn0;
                 return 0;
         case IP_VERSION(3, 1, 1):
         case IP_VERSION(3, 1, 2):
@@ -993,9 +1044,19 @@ static int nv_common_late_init(void *handle)

         if (amdgpu_sriov_vf(adev)) {
                 xgpu_nv_mailbox_get_irq(adev);
-               amdgpu_virt_update_sriov_video_codec(adev,
-                               sriov_sc_video_codecs_encode_array, ARRAY_SIZE(sriov_sc_video_codecs_encode_array),
-                               sriov_sc_video_codecs_decode_array, ARRAY_SIZE(sriov_sc_video_codecs_decode_array));
+               if (adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) {
+                       amdgpu_virt_update_sriov_video_codec(adev,
+                                                            sriov_sc_video_codecs_encode_array,
+                                                            ARRAY_SIZE(sriov_sc_video_codecs_encode_array),
+                                                            sriov_sc_video_codecs_decode_array_vcn1,
+                                                            ARRAY_SIZE(sriov_sc_video_codecs_decode_array_vcn1));
+               } else {
+                       amdgpu_virt_update_sriov_video_codec(adev,
+                                                            sriov_sc_video_codecs_encode_array,
+                                                            ARRAY_SIZE(sriov_sc_video_codecs_encode_array),
+                                                            sriov_sc_video_codecs_decode_array_vcn1,
+                                                            ARRAY_SIZE(sriov_sc_video_codecs_decode_array_vcn1));
+               }
         }

         return 0;
--
2.39.0





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