On Mon, Jan 16, 2023 at 3:12 PM Christian König
<ckoenig.leichtzumerken@xxxxxxxxx> wrote:
>
> We only need one offset and not an array of it.
>
> We have a wait in the amdgpu_bo_kmap() code for quite a while now, so
> waiting here isn't needed any more.
This should probably be two patches, one to clean up the offsets and
one to remove the syncs.
Alex
>
> Signed-off-by: Christian König <christian.koenig@xxxxxxx>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 38 +++++++------------------
> 1 file changed, 10 insertions(+), 28 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
> index b67a5fb2ff3e..229419c0c031 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
> @@ -1118,30 +1118,26 @@ static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo,
> {
> struct amdgpu_device *adev = ring->adev;
> struct dma_fence *f = NULL;
> + uint32_t offset, data[4];
> struct amdgpu_job *job;
> struct amdgpu_ib *ib;
> - uint32_t data[4];
> uint64_t addr;
> - long r;
> - int i;
> - unsigned offset_idx = 0;
> - unsigned offset[3] = { UVD_BASE_SI, 0, 0 };
> + int i, r;
>
> r = amdgpu_job_alloc_with_ib(adev, 64, direct ? AMDGPU_IB_POOL_DIRECT :
> AMDGPU_IB_POOL_DELAYED, &job);
> if (r)
> return r;
>
> - if (adev->asic_type >= CHIP_VEGA10) {
> - offset_idx = 1 + ring->me;
> - offset[1] = adev->reg_offset[UVD_HWIP][0][1];
> - offset[2] = adev->reg_offset[UVD_HWIP][1][1];
> - }
> + if (adev->asic_type >= CHIP_VEGA10)
> + offset = adev->reg_offset[UVD_HWIP][ring->me][1];
> + else
> + offset = UVD_BASE_SI;
>
> - data[0] = PACKET0(offset[offset_idx] + UVD_GPCOM_VCPU_DATA0, 0);
> - data[1] = PACKET0(offset[offset_idx] + UVD_GPCOM_VCPU_DATA1, 0);
> - data[2] = PACKET0(offset[offset_idx] + UVD_GPCOM_VCPU_CMD, 0);
> - data[3] = PACKET0(offset[offset_idx] + UVD_NO_OP, 0);
> + data[0] = PACKET0(offset + UVD_GPCOM_VCPU_DATA0, 0);
> + data[1] = PACKET0(offset + UVD_GPCOM_VCPU_DATA1, 0);
> + data[2] = PACKET0(offset + UVD_GPCOM_VCPU_CMD, 0);
> + data[3] = PACKET0(offset + UVD_NO_OP, 0);
>
> ib = &job->ibs[0];
> addr = amdgpu_bo_gpu_offset(bo);
> @@ -1158,24 +1154,10 @@ static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo,
> ib->length_dw = 16;
>
> if (direct) {
> - r = dma_resv_wait_timeout(bo->tbo.base.resv,
> - DMA_RESV_USAGE_KERNEL, false,
> - msecs_to_jiffies(10));
> - if (r == 0)
> - r = -ETIMEDOUT;
> - if (r < 0)
> - goto err_free;
> -
> r = amdgpu_job_submit_direct(job, ring, &f);
> if (r)
> goto err_free;
> } else {
> - r = amdgpu_sync_resv(adev, &job->sync, bo->tbo.base.resv,
> - AMDGPU_SYNC_ALWAYS,
> - AMDGPU_FENCE_OWNER_UNDEFINED);
> - if (r)
> - goto err_free;
> -
> r = amdgpu_job_submit(job, &adev->uvd.entity,
> AMDGPU_FENCE_OWNER_UNDEFINED, &f);
> if (r)
> --
> 2.34.1
>
