On Tue, Jan 10, 2023 at 10:44 AM Rodrigo Siqueira <Rodrigo.Siqueira@xxxxxxx> wrote: > > It was reported that on kernel v6.2-rc1, we have the following stack > size issue: > > make[3]: *** [/kisskb/src/scripts/Makefile.build:504: drivers/media] > Error 2 > [...]/display/dc/dml/dcn31/display_mode_vba_31.c: In function > 'UseMinimumDCFCLK': > [...]/display/dc/dml/dcn31/display_mode_vba_31.c:7082:1: error: the > frame size of 2224 bytes is larger than 2048 bytes > [-Werror=frame-larger-than=] > > This commit introduces a new struct that will accommodate some internal > variables under the UseMinimumDCFCLK function. This change is the first > of a series of patches that gradually move each of the arrays of double > to the new struct to reduce the stack size for DCN31 and DCN314. > > Cc: Alex Deucher <alexdeucher@xxxxxxxxx> > Cc: Aurabindo Pillai <aurabindo.pillai@xxxxxxx> > Cc: Hamza Mahfooz <hamza.mahfooz@xxxxxxx> > Cc: Roman Li <roman.li@xxxxxxx> > Cc: Geert Uytterhoeven <geert@xxxxxxxxxxxxxx> > Link: https://lore.kernel.org/all/20221227082932.798359-1-geert@xxxxxxxxxxxxxx/ > Reported-by: Geert Uytterhoeven <geert@xxxxxxxxxxxxxx> > Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@xxxxxxx> Series is: Acked-by: Alex Deucher <alexander.deucher@xxxxxxx> > --- > .../gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c | 7 +++---- > drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h | 5 +++++ > 2 files changed, 8 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c > index ec351c8418cb..00d3c57f0d98 100644 > --- a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c > +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c > @@ -6928,7 +6928,6 @@ static void UseMinimumDCFCLK( > struct vba_vars_st *v = &mode_lib->vba; > int dummy1, i, j, k; > double NormalEfficiency, dummy2, dummy3; > - double TotalMaxPrefetchFlipDPTERowBandwidth[DC__VOLTAGE_STATES][2]; > > NormalEfficiency = v->PercentOfIdealFabricAndSDPPortBWReceivedAfterUrgLatency / 100.0; > for (i = 0; i < v->soc.num_states; ++i) { > @@ -6947,9 +6946,9 @@ static void UseMinimumDCFCLK( > int NoOfDPPState[DC__NUM_DPP__MAX]; > double MinimumTvmPlus2Tr0; > > - TotalMaxPrefetchFlipDPTERowBandwidth[i][j] = 0; > + v->UseMinimumDCFCLK_stack_reduction.TotalMaxPrefetchFlipDPTERowBandwidth[i][j] = 0; > for (k = 0; k < v->NumberOfActivePlanes; ++k) { > - TotalMaxPrefetchFlipDPTERowBandwidth[i][j] = TotalMaxPrefetchFlipDPTERowBandwidth[i][j] > + v->UseMinimumDCFCLK_stack_reduction.TotalMaxPrefetchFlipDPTERowBandwidth[i][j] = v->UseMinimumDCFCLK_stack_reduction.TotalMaxPrefetchFlipDPTERowBandwidth[i][j] > + v->NoOfDPP[i][j][k] * v->DPTEBytesPerRow[i][j][k] / (15.75 * v->HTotal[k] / v->PixelClock[k]); > } > > @@ -6960,7 +6959,7 @@ static void UseMinimumDCFCLK( > MinimumTWait = CalculateTWait(MaxPrefetchMode, v->FinalDRAMClockChangeLatency, v->UrgLatency[i], v->SREnterPlusExitTime); > NonDPTEBandwidth = v->TotalVActivePixelBandwidth[i][j] + v->TotalVActiveCursorBandwidth[i][j] + v->TotalMetaRowBandwidth[i][j]; > DPTEBandwidth = (v->HostVMEnable == true || v->ImmediateFlipRequirement[0] == dm_immediate_flip_required) ? > - TotalMaxPrefetchFlipDPTERowBandwidth[i][j] : v->TotalDPTERowBandwidth[i][j]; > + v->UseMinimumDCFCLK_stack_reduction.TotalMaxPrefetchFlipDPTERowBandwidth[i][j] : v->TotalDPTERowBandwidth[i][j]; > DCFCLKRequiredForAverageBandwidth = dml_max3( > v->ProjectedDCFCLKDeepSleep[i][j], > (NonDPTEBandwidth + v->TotalDPTERowBandwidth[i][j]) / v->ReturnBusWidth > diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h > index 81e53e67cd0b..660c22a19c8d 100644 > --- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h > +++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h > @@ -249,6 +249,10 @@ struct dml32_ModeSupportAndSystemConfigurationFull { > bool dummy_boolean[2]; > }; > > +struct UseMinimumDCFCLK_vars { > + double TotalMaxPrefetchFlipDPTERowBandwidth[DC__VOLTAGE_STATES][2]; > +}; > + > struct dummy_vars { > struct DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation > DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation; > @@ -1236,6 +1240,7 @@ struct vba_vars_st { > bool VActiveBandwithSupport[DC__VOLTAGE_STATES][2]; > bool NotEnoughDETSwathFillLatencyHidingPerState[DC__VOLTAGE_STATES][2]; > struct dummy_vars dummy_vars; > + struct UseMinimumDCFCLK_vars UseMinimumDCFCLK_stack_reduction; > }; > > bool CalculateMinAndMaxPrefetchMode( > -- > 2.39.0 >
