It was reported that on kernel v6.2-rc1, we have the following stack size issue: make[3]: *** [/kisskb/src/scripts/Makefile.build:504: drivers/media] Error 2 [...]/display/dc/dml/dcn31/display_mode_vba_31.c: In function 'UseMinimumDCFCLK': [...]/display/dc/dml/dcn31/display_mode_vba_31.c:7082:1: error: the frame size of 2224 bytes is larger than 2048 bytes [-Werror=frame-larger-than=] This commit move DCFCLKRequiredForPeakBandwidthPerPlane from UseMinimumDCFCLK to reduce the stack size. Cc: Alex Deucher <alexdeucher@xxxxxxxxx> Cc: Aurabindo Pillai <aurabindo.pillai@xxxxxxx> Cc: Hamza Mahfooz <hamza.mahfooz@xxxxxxx> Cc: Roman Li <roman.li@xxxxxxx> Cc: Geert Uytterhoeven <geert@xxxxxxxxxxxxxx> Link: https://lore.kernel.org/all/20221227082932.798359-1-geert@xxxxxxxxxxxxxx/ Reported-by: Geert Uytterhoeven <geert@xxxxxxxxxxxxxx> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@xxxxxxx> --- .../display/dc/dml/dcn31/display_mode_vba_31.c | 15 +++++++-------- .../gpu/drm/amd/display/dc/dml/display_mode_vba.h | 1 + 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c index 28dcd46a28c0..8175f3603f00 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c @@ -6932,7 +6932,6 @@ static void UseMinimumDCFCLK( NormalEfficiency = v->PercentOfIdealFabricAndSDPPortBWReceivedAfterUrgLatency / 100.0; for (i = 0; i < v->soc.num_states; ++i) { for (j = 0; j <= 1; ++j) { - double DCFCLKRequiredForPeakBandwidthPerPlane[DC__NUM_DPP__MAX]; double DynamicMetadataVMExtraLatency[DC__NUM_DPP__MAX]; double MinimumTWait; double NonDPTEBandwidth; @@ -7006,14 +7005,14 @@ static void UseMinimumDCFCLK( double ExpectedVRatioPrefetch; ExpectedVRatioPrefetch = v->UseMinimumDCFCLK_stack_reduction.PrefetchPixelLinesTime[k] / (PrefetchTime * v->UseMinimumDCFCLK_stack_reduction.PixelDCFCLKCyclesRequiredInPrefetch[k] / DCFCLKCyclesRequiredInPrefetch); - DCFCLKRequiredForPeakBandwidthPerPlane[k] = NoOfDPPState[k] * v->UseMinimumDCFCLK_stack_reduction.PixelDCFCLKCyclesRequiredInPrefetch[k] / v->UseMinimumDCFCLK_stack_reduction.PrefetchPixelLinesTime[k] + v->UseMinimumDCFCLK_stack_reduction.DCFCLKRequiredForPeakBandwidthPerPlane[k] = NoOfDPPState[k] * v->UseMinimumDCFCLK_stack_reduction.PixelDCFCLKCyclesRequiredInPrefetch[k] / v->UseMinimumDCFCLK_stack_reduction.PrefetchPixelLinesTime[k] * dml_max(1.0, ExpectedVRatioPrefetch) * dml_max(1.0, ExpectedVRatioPrefetch / 4) * ExpectedPrefetchBWAcceleration; if (v->HostVMEnable == true || v->ImmediateFlipRequirement[0] == dm_immediate_flip_required) { - DCFCLKRequiredForPeakBandwidthPerPlane[k] = DCFCLKRequiredForPeakBandwidthPerPlane[k] + v->UseMinimumDCFCLK_stack_reduction.DCFCLKRequiredForPeakBandwidthPerPlane[k] = v->UseMinimumDCFCLK_stack_reduction.DCFCLKRequiredForPeakBandwidthPerPlane[k] + NoOfDPPState[k] * DPTEBandwidth / NormalEfficiency / NormalEfficiency / v->ReturnBusWidth; } } else { - DCFCLKRequiredForPeakBandwidthPerPlane[k] = v->DCFCLKPerState[i]; + v->UseMinimumDCFCLK_stack_reduction.DCFCLKRequiredForPeakBandwidthPerPlane[k] = v->DCFCLKPerState[i]; } if (v->DynamicMetadataEnable[k] == true) { double TSetupPipe; @@ -7044,17 +7043,17 @@ static void UseMinimumDCFCLK( AllowedTimeForUrgentExtraLatency = v->MaximumVStartup[i][j][k] * v->HTotal[k] / v->PixelClock[k] - MinimumTWait - TSetupPipe - TdmbfPipe - TdmecPipe - TdmsksPipe - DynamicMetadataVMExtraLatency[k]; if (AllowedTimeForUrgentExtraLatency > 0) { - DCFCLKRequiredForPeakBandwidthPerPlane[k] = dml_max( - DCFCLKRequiredForPeakBandwidthPerPlane[k], + v->UseMinimumDCFCLK_stack_reduction.DCFCLKRequiredForPeakBandwidthPerPlane[k] = dml_max( + v->UseMinimumDCFCLK_stack_reduction.DCFCLKRequiredForPeakBandwidthPerPlane[k], ExtraLatencyCycles / AllowedTimeForUrgentExtraLatency); } else { - DCFCLKRequiredForPeakBandwidthPerPlane[k] = v->DCFCLKPerState[i]; + v->UseMinimumDCFCLK_stack_reduction.DCFCLKRequiredForPeakBandwidthPerPlane[k] = v->DCFCLKPerState[i]; } } } DCFCLKRequiredForPeakBandwidth = 0; for (k = 0; k <= v->NumberOfActivePlanes - 1; ++k) { - DCFCLKRequiredForPeakBandwidth = DCFCLKRequiredForPeakBandwidth + DCFCLKRequiredForPeakBandwidthPerPlane[k]; + DCFCLKRequiredForPeakBandwidth = DCFCLKRequiredForPeakBandwidth + v->UseMinimumDCFCLK_stack_reduction.DCFCLKRequiredForPeakBandwidthPerPlane[k]; } MinimumTvmPlus2Tr0 = v->UrgLatency[i] * (v->GPUVMEnable == true ? diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h index 733947be3737..4c5206bfad38 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h +++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h @@ -253,6 +253,7 @@ struct UseMinimumDCFCLK_vars { double TotalMaxPrefetchFlipDPTERowBandwidth[DC__VOLTAGE_STATES][2]; double PixelDCFCLKCyclesRequiredInPrefetch[DC__NUM_DPP__MAX]; double PrefetchPixelLinesTime[DC__NUM_DPP__MAX]; + double DCFCLKRequiredForPeakBandwidthPerPlane[DC__NUM_DPP__MAX]; }; struct dummy_vars { -- 2.39.0
