It looks like this patch never landed.
Alex
On Tue, Oct 11, 2022 at 9:48 PM Zhang, Yifan <Yifan1.Zhang@xxxxxxx> wrote:
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> [Public]
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>
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> This patch is
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>
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> Reviewed-by: Yifan Zhang <yifan1.zhang@xxxxxxx>
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> From: Zhang, Jesse(Jie) <Jesse.Zhang@xxxxxxx>
> Sent: Tuesday, October 11, 2022 1:23 PM
> To: amd-gfx@xxxxxxxxxxxxxxxxxxxxx
> Cc: Deucher, Alexander <Alexander.Deucher@xxxxxxx>; Zhang, Yifan <Yifan1.Zhang@xxxxxxx>; Kuehling, Felix <Felix.Kuehling@xxxxxxx>
> Subject: RE: [PATCH] drm/amdkfd: correct the cache info for gfx1036
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>
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> [AMD Official Use Only - General]
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>
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> correct the cache information for gfx1036
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>
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> Signed-off-by: Yifan Zhang yifan1.zhang@xxxxxxx
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>
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> Signed-off-by: jie1zhan jesse.zhang@xxxxxxx
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> Change-Id: I60e754737057c144e69a6511ba6ddfca472ca7a1
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>
>
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
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> index 477a30981c1b..d25ac9cbe5b2 100644
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> --- a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
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> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
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> @@ -795,6 +795,54 @@ static struct kfd_gpu_cache_info yellow_carp_cache_info[] = {
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> },
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> };
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>
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> +static struct kfd_gpu_cache_info gc_10_3_6_cache_info[] = {
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> + {
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> + /* TCP L1 Cache per CU */
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> + .cache_size = 16,
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> + .cache_level = 1,
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> + .flags = (CRAT_CACHE_FLAGS_ENABLED |
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> + CRAT_CACHE_FLAGS_DATA_CACHE |
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> + CRAT_CACHE_FLAGS_SIMD_CACHE),
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> + .num_cu_shared = 1,
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> + },
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> + {
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> + /* Scalar L1 Instruction Cache per SQC */
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> + .cache_size = 32,
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> + .cache_level = 1,
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> + .flags = (CRAT_CACHE_FLAGS_ENABLED |
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> + CRAT_CACHE_FLAGS_INST_CACHE |
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> + CRAT_CACHE_FLAGS_SIMD_CACHE),
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> + .num_cu_shared = 2,
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> + },
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> + {
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> + /* Scalar L1 Data Cache per SQC */
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> + .cache_size = 16,
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> + .cache_level = 1,
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> + .flags = (CRAT_CACHE_FLAGS_ENABLED |
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> + CRAT_CACHE_FLAGS_DATA_CACHE |
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> + CRAT_CACHE_FLAGS_SIMD_CACHE),
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> + .num_cu_shared = 2,
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> + },
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> + {
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> + /* GL1 Data Cache per SA */
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> + .cache_size = 128,
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> + .cache_level = 1,
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> + .flags = (CRAT_CACHE_FLAGS_ENABLED |
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> + CRAT_CACHE_FLAGS_DATA_CACHE |
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> + CRAT_CACHE_FLAGS_SIMD_CACHE),
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> + .num_cu_shared = 2,
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> + },
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> + {
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> + /* L2 Data Cache per GPU (Total Tex Cache) */
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> + .cache_size = 256,
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> + .cache_level = 2,
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> + .flags = (CRAT_CACHE_FLAGS_ENABLED |
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> + CRAT_CACHE_FLAGS_DATA_CACHE |
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> + CRAT_CACHE_FLAGS_SIMD_CACHE),
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> + .num_cu_shared = 2,
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> + },
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> +};
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> +
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> static void kfd_populated_cu_info_cpu(struct kfd_topology_device *dev,
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> struct crat_subtype_computeunit *cu)
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> {
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> @@ -1514,11 +1562,14 @@ static int kfd_fill_gpu_cache_info(struct kfd_dev *kdev,
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> num_of_cache_types = ARRAY_SIZE(beige_goby_cache_info);
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> break;
>
> case IP_VERSION(10, 3, 3):
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> - case IP_VERSION(10, 3, 6): /* TODO: Double check these on production silicon */
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> case IP_VERSION(10, 3, 7): /* TODO: Double check these on production silicon */
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> pcache_info = yellow_carp_cache_info;
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> num_of_cache_types = ARRAY_SIZE(yellow_carp_cache_info);
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> break;
>
> + case IP_VERSION(10, 3, 6):
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> + pcache_info = gc_10_3_6_cache_info;
>
> + num_of_cache_types = ARRAY_SIZE(gc_10_3_6_cache_info);
>
> + break;
>
> case IP_VERSION(11, 0, 0):
