Series is reviewed-by: Evan Quan <evan.quan@xxxxxxx>
> -----Original Message-----
> From: amd-gfx <amd-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx> On Behalf Of
> Alexey Kodanev
> Sent: Tuesday, October 4, 2022 4:14 PM
> To: amd-gfx@xxxxxxxxxxxxxxxxxxxxx
> Cc: Alexey Kodanev <aleksei.kodanev@xxxxxxxxxxx>
> Subject: [PATCH 2/2] drm/amd/pm: smu7_hwmgr: fix potential off-by-one
> overflow in 'performance_levels'
>
> Since 'hardwareActivityPerformanceLevels' is set to the size of the
> 'performance_levels' array in smu7_hwmgr_backend_init(), using the '<='
> assertion to check for the next index value is incorrect.
> Replace it with '<'.
>
> Detected using the static analysis tool - Svace.
> Fixes: 599a7e9fe1b6 ("drm/amd/powerplay: implement smu7 hwmgr to
> manager asics with smu ip version 7.")
> Signed-off-by: Alexey Kodanev <aleksei.kodanev@xxxxxxxxxxx>
> ---
> drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
> b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
> index e4fcbf8a7eb5..7ef7e81525a3 100644
> --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
> +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
> @@ -3603,7 +3603,7 @@ static int
> smu7_get_pp_table_entry_callback_func_v1(struct pp_hwmgr *hwmgr,
> return -EINVAL);
>
> PP_ASSERT_WITH_CODE(
> - (smu7_power_state->performance_level_count <=
> + (smu7_power_state->performance_level_count <
> hwmgr-
> >platform_descriptor.hardwareActivityPerformanceLevels),
> "Performance levels exceeds Driver limit!",
> return -EINVAL);
> --
> 2.25.1
