Am 2022-10-05 um 07:03 schrieb Danijel Slivka:
CPU pagetable updates have issues with HDP flush as VF MMIO access
protection is not allowing write during sriov runtime to
mmBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL
Signed-off-by: Danijel Slivka <danijel.slivka@xxxxxxx>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 83b0c5d86e48..32088ac0666c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -2338,7 +2338,9 @@ void amdgpu_vm_manager_init(struct amdgpu_device *adev)
*/
#ifdef CONFIG_X86_64
if (amdgpu_vm_update_mode == -1) {
- if (amdgpu_gmc_vram_full_visible(&adev->gmc))
+ if (amdgpu_gmc_vram_full_visible(&adev->gmc) &&
+ !(adev->asic_type == CHIP_SIENNA_CICHLID &&
+ amdgpu_sriov_vf(adev)))
This would need at least a code comment. But I'd prefer a more general
solution that expresses that some ASICs don't allow any MMIO access
under SRIOV.
I found that there is this function defined in amdgpu_virt.c/h: bool
amdgpu_virt_mmio_blocked(struct amdgpu_device *adev). Would this return
the correct result and could you use it here instead of a hard-coded
asic_type?
Or maybe this could be added as a flag in (adev)->virt.caps and get
initialized in some ASIC-specific code path.
Regards,
Felix
adev->vm_manager.vm_update_mode =
AMDGPU_VM_USE_CPU_FOR_COMPUTE;
else
