[AMD Official Use Only - General]
> -----Original Message-----
> From: Kuehling, Felix <Felix.Kuehling@xxxxxxx>
> Sent: Friday, August 12, 2022 5:27 PM
> To: Joshi, Mukul <Mukul.Joshi@xxxxxxx>; amd-gfx@xxxxxxxxxxxxxxxxxxxxx
> Subject: Re: [PATCH] drm/amdgpu: Fix interrupt handling on ih_soft ring
>
>
> On 2022-08-12 16:56, Mukul Joshi wrote:
> > There are no backing hardware registers for ih_soft ring.
> > As a result, don't try to access hardware registers for read and write
> > pointers when processing interrupts on the IH soft ring.
> >
> > Signed-off-by: Mukul Joshi <mukul.joshi@xxxxxxx>
>
> The patch looks good to me. But you probably should apply the same
> changes to vega10_ih.c and navi10_ih.c as well.
>
Oops sorry I missed that. Will update the patch and re-send.
Regards,
Mukul
> Regards,
> Felix
>
>
> > ---
> > drivers/gpu/drm/amd/amdgpu/vega20_ih.c | 7 ++++++-
> > 1 file changed, 6 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/vega20_ih.c
> > b/drivers/gpu/drm/amd/amdgpu/vega20_ih.c
> > index 3b4eb8285943..2022ffbb8dba 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/vega20_ih.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/vega20_ih.c
> > @@ -385,9 +385,11 @@ static u32 vega20_ih_get_wptr(struct
> amdgpu_device *adev,
> > u32 wptr, tmp;
> > struct amdgpu_ih_regs *ih_regs;
> >
> > - if (ih == &adev->irq.ih) {
> > + if (ih == &adev->irq.ih || ih == &adev->irq.ih_soft) {
> > /* Only ring0 supports writeback. On other rings fall back
> > * to register-based code with overflow checking below.
> > + * ih_soft ring doesn't have any backing hardware registers,
> > + * update wptr and return.
> > */
> > wptr = le32_to_cpu(*ih->wptr_cpu);
> >
> > @@ -461,6 +463,9 @@ static void vega20_ih_set_rptr(struct
> amdgpu_device *adev,
> > {
> > struct amdgpu_ih_regs *ih_regs;
> >
> > + if (ih == &adev->irq.ih_soft)
> > + return;
> > +
> > if (ih->use_doorbell) {
> > /* XXX check if swapping is necessary on BE */
> > *ih->rptr_cpu = ih->rptr;
