Re: [PATCH 5/5] drm/amd/display: move FPU code from dcn301 clk mgr to DML folder

[Rodrigo Siqueira Jordao <Rodrigo.Siqueira@xxxxxxx>]

On 2022-07-21 13:26, Maíra Canal wrote:
> Hi Melissa,
>
> On 7/20/22 16:32, Melissa Wen wrote:
> > The -mno-gnu-attribute option in dcn301 clk mgr makefile hides a soft vs
> > hard fp error for powerpc. After removing this flag, we can see some FPU
> > code remains there:
> >
> > gcc-11.3.0-nolibc/powerpc64-linux/bin/powerpc64-linux-ld:
> > drivers/gpu/drm/amd/amdgpu/../display/dc/dml/display_mode_lib.o uses
> > hard float,
> > drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn301/vg_clk_mgr.o
> > uses soft float
> >
> > Therefore, remove the -mno-gnu-attribute flag for dcn301/powerpc and
> > move FPU-associated code to DML folder.
> >
> > Signed-off-by: Melissa Wen <mwen@xxxxxxxxxx>
> > ---
> >   .../gpu/drm/amd/display/dc/clk_mgr/Makefile   |  6 --
> >   .../display/dc/clk_mgr/dcn301/vg_clk_mgr.c    | 86 ++-----------------
> >   .../display/dc/clk_mgr/dcn301/vg_clk_mgr.h    |  3 +
> >   .../amd/display/dc/dml/dcn301/dcn301_fpu.c    | 74 ++++++++++++++++
> >   4 files changed, 84 insertions(+), 85 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile b/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile
> > index 15b660a951a5..271d8e573181 100644
> > --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile
> > +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile
> > @@ -123,12 +123,6 @@ AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN30)
> >   ###############################################################################
> >   CLK_MGR_DCN301 = vg_clk_mgr.o dcn301_smu.o
> >   
> > -# prevent build errors regarding soft-float vs hard-float FP ABI tags
> > -# this code is currently unused on ppc64, as it applies to VanGogh APUs only
> > -ifdef CONFIG_PPC64
> > -CFLAGS_$(AMDDALPATH)/dc/clk_mgr/dcn301/vg_clk_mgr.o := $(call cc-option,-mno-gnu-attribute)
> > -endif
> > -
> >   AMD_DAL_CLK_MGR_DCN301 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dcn301/,$(CLK_MGR_DCN301))
> >   
> >   AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN301)
> > diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c
> > index f310b0d25a07..65f224af03c0 100644
> > --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c
> > +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c
> > @@ -32,6 +32,10 @@
> >   // For dcn20_update_clocks_update_dpp_dto
> >   #include "dcn20/dcn20_clk_mgr.h"
> >   
> > +// For DML FPU code
> > +#include "dml/dcn20/dcn20_fpu.h"
> > +#include "dml/dcn301/dcn301_fpu.h"
> > +
>
> I guess the "dml/dcn301/dcn301_fpu.h" header is not needed, as you only
> use dcn21_clk_mgr_set_bw_params_wm_table and the structs are on the
> source file.
>
> Besides that, to the whole series:
> Reviewed-by: Maíra Canal <mairacanal@xxxxxxxxxx>
>
> Best Regards,
> - Maíra Canal

Nice catch!
I'll make this adjustment before I merge it.

Thanks
Siqueira

> >   #include "vg_clk_mgr.h"
> >   #include "dcn301_smu.h"
> >   #include "reg_helper.h"
> > @@ -526,81 +530,6 @@ static struct clk_bw_params vg_bw_params = {
> >   
> >   };
> >   
> > -static struct wm_table ddr4_wm_table = {
> > -	.entries = {
> > -		{
> > -			.wm_inst = WM_A,
> > -			.wm_type = WM_TYPE_PSTATE_CHG,
> > -			.pstate_latency_us = 11.72,
> > -			.sr_exit_time_us = 6.09,
> > -			.sr_enter_plus_exit_time_us = 7.14,
> > -			.valid = true,
> > -		},
> > -		{
> > -			.wm_inst = WM_B,
> > -			.wm_type = WM_TYPE_PSTATE_CHG,
> > -			.pstate_latency_us = 11.72,
> > -			.sr_exit_time_us = 10.12,
> > -			.sr_enter_plus_exit_time_us = 11.48,
> > -			.valid = true,
> > -		},
> > -		{
> > -			.wm_inst = WM_C,
> > -			.wm_type = WM_TYPE_PSTATE_CHG,
> > -			.pstate_latency_us = 11.72,
> > -			.sr_exit_time_us = 10.12,
> > -			.sr_enter_plus_exit_time_us = 11.48,
> > -			.valid = true,
> > -		},
> > -		{
> > -			.wm_inst = WM_D,
> > -			.wm_type = WM_TYPE_PSTATE_CHG,
> > -			.pstate_latency_us = 11.72,
> > -			.sr_exit_time_us = 10.12,
> > -			.sr_enter_plus_exit_time_us = 11.48,
> > -			.valid = true,
> > -		},
> > -	}
> > -};
> > -
> > -static struct wm_table lpddr5_wm_table = {
> > -	.entries = {
> > -		{
> > -			.wm_inst = WM_A,
> > -			.wm_type = WM_TYPE_PSTATE_CHG,
> > -			.pstate_latency_us = 11.65333,
> > -			.sr_exit_time_us = 13.5,
> > -			.sr_enter_plus_exit_time_us = 16.5,
> > -			.valid = true,
> > -		},
> > -		{
> > -			.wm_inst = WM_B,
> > -			.wm_type = WM_TYPE_PSTATE_CHG,
> > -			.pstate_latency_us = 11.65333,
> > -			.sr_exit_time_us = 13.5,
> > -			.sr_enter_plus_exit_time_us = 16.5,
> > -			.valid = true,
> > -		},
> > -		{
> > -			.wm_inst = WM_C,
> > -			.wm_type = WM_TYPE_PSTATE_CHG,
> > -			.pstate_latency_us = 11.65333,
> > -			.sr_exit_time_us = 13.5,
> > -			.sr_enter_plus_exit_time_us = 16.5,
> > -			.valid = true,
> > -		},
> > -		{
> > -			.wm_inst = WM_D,
> > -			.wm_type = WM_TYPE_PSTATE_CHG,
> > -			.pstate_latency_us = 11.65333,
> > -			.sr_exit_time_us = 13.5,
> > -			.sr_enter_plus_exit_time_us = 16.5,
> > -			.valid = true,
> > -		},
> > -	}
> > -};
> > -
> > -
> >   static unsigned int find_dcfclk_for_voltage(const struct vg_dpm_clocks *clock_table,
> >   		unsigned int voltage)
> >   {
> > @@ -670,10 +599,9 @@ static void vg_clk_mgr_helper_populate_bw_params(
> >   		/*
> >   		 * WM set D will be re-purposed for memory retraining
> >   		 */
> > -		bw_params->wm_table.entries[WM_D].pstate_latency_us = LPDDR_MEM_RETRAIN_LATENCY;
> > -		bw_params->wm_table.entries[WM_D].wm_inst = WM_D;
> > -		bw_params->wm_table.entries[WM_D].wm_type = WM_TYPE_RETRAINING;
> > -		bw_params->wm_table.entries[WM_D].valid = true;
> > +		DC_FP_START();
> > +		dcn21_clk_mgr_set_bw_params_wm_table(bw_params);
> > +		DC_FP_END();
> >   	}
> >   
> >   }
> > diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.h
> > index 7255477307f1..75884f572989 100644
> > --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.h
> > +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.h
> > @@ -29,6 +29,9 @@
> >   
> >   struct watermarks;
> >   
> > +extern struct wm_table ddr4_wm_table;
> > +extern struct wm_table lpddr5_wm_table;
> > +
> >   struct smu_watermark_set {
> >   	struct watermarks *wm_set;
> >   	union large_integer mc_address;
> > diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c
> > index e4863f0bf0f6..7ef66e511ec8 100644
> > --- a/drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c
> > +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c
> > @@ -214,6 +214,80 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_01_soc = {
> >   	.urgent_latency_adjustment_fabric_clock_reference_mhz = 0,
> >   };
> >   
> > +struct wm_table ddr4_wm_table = {
> > +	.entries = {
> > +		{
> > +			.wm_inst = WM_A,
> > +			.wm_type = WM_TYPE_PSTATE_CHG,
> > +			.pstate_latency_us = 11.72,
> > +			.sr_exit_time_us = 6.09,
> > +			.sr_enter_plus_exit_time_us = 7.14,
> > +			.valid = true,
> > +		},
> > +		{
> > +			.wm_inst = WM_B,
> > +			.wm_type = WM_TYPE_PSTATE_CHG,
> > +			.pstate_latency_us = 11.72,
> > +			.sr_exit_time_us = 10.12,
> > +			.sr_enter_plus_exit_time_us = 11.48,
> > +			.valid = true,
> > +		},
> > +		{
> > +			.wm_inst = WM_C,
> > +			.wm_type = WM_TYPE_PSTATE_CHG,
> > +			.pstate_latency_us = 11.72,
> > +			.sr_exit_time_us = 10.12,
> > +			.sr_enter_plus_exit_time_us = 11.48,
> > +			.valid = true,
> > +		},
> > +		{
> > +			.wm_inst = WM_D,
> > +			.wm_type = WM_TYPE_PSTATE_CHG,
> > +			.pstate_latency_us = 11.72,
> > +			.sr_exit_time_us = 10.12,
> > +			.sr_enter_plus_exit_time_us = 11.48,
> > +			.valid = true,
> > +		},
> > +	}
> > +};
> > +
> > +struct wm_table lpddr5_wm_table = {
> > +	.entries = {
> > +		{
> > +			.wm_inst = WM_A,
> > +			.wm_type = WM_TYPE_PSTATE_CHG,
> > +			.pstate_latency_us = 11.65333,
> > +			.sr_exit_time_us = 13.5,
> > +			.sr_enter_plus_exit_time_us = 16.5,
> > +			.valid = true,
> > +		},
> > +		{
> > +			.wm_inst = WM_B,
> > +			.wm_type = WM_TYPE_PSTATE_CHG,
> > +			.pstate_latency_us = 11.65333,
> > +			.sr_exit_time_us = 13.5,
> > +			.sr_enter_plus_exit_time_us = 16.5,
> > +			.valid = true,
> > +		},
> > +		{
> > +			.wm_inst = WM_C,
> > +			.wm_type = WM_TYPE_PSTATE_CHG,
> > +			.pstate_latency_us = 11.65333,
> > +			.sr_exit_time_us = 13.5,
> > +			.sr_enter_plus_exit_time_us = 16.5,
> > +			.valid = true,
> > +		},
> > +		{
> > +			.wm_inst = WM_D,
> > +			.wm_type = WM_TYPE_PSTATE_CHG,
> > +			.pstate_latency_us = 11.65333,
> > +			.sr_exit_time_us = 13.5,
> > +			.sr_enter_plus_exit_time_us = 16.5,
> > +			.valid = true,
> > +		},
> > +	}
> > +};
> > +
> >   static void calculate_wm_set_for_vlevel(int vlevel,
> >   		struct wm_range_table_entry *table_entry,
> >   		struct dcn_watermarks *wm_set,