>From VCN4, AMDGPU_HW_IP_VCN_UNIFIED is used to support both encoding and decoding jobs, it re-uses the same queue number of AMDGPU_HW_IP_VCN_ENC. link: https://gitlab.freedesktop.org/mesa/drm/-/merge_requests/245/commits Signed-off-by: Ruijing Dong <ruijing.dong@xxxxxxx> --- include/uapi/drm/amdgpu_drm.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h index 18d3246d636e..e268cd3cdb12 100644 --- a/include/uapi/drm/amdgpu_drm.h +++ b/include/uapi/drm/amdgpu_drm.h @@ -560,6 +560,12 @@ struct drm_amdgpu_gem_va { #define AMDGPU_HW_IP_UVD_ENC 5 #define AMDGPU_HW_IP_VCN_DEC 6 #define AMDGPU_HW_IP_VCN_ENC 7 +/** + * From VCN4, AMDGPU_HW_IP_VCN_UNIFIED is used to support + * both encoding and decoding jobs, it re-uses the same + * queue number of AMDGPU_HW_IP_VCN_ENC. + */ +#define AMDGPU_HW_IP_VCN_UNIFIED AMDGPU_HW_IP_VCN_ENC #define AMDGPU_HW_IP_VCN_JPEG 8 #define AMDGPU_HW_IP_NUM 9 -- 2.25.1
