[AMD Official Use Only - General]
Series is Reviewed-by: Kent Russell <kent.russell@xxxxxxx>
> -----Original Message-----
> From: amd-gfx <amd-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx> On Behalf Of Alex
> Deucher
> Sent: Wednesday, July 13, 2022 2:01 PM
> To: amd-gfx@xxxxxxxxxxxxxxxxxxxxx
> Cc: Deucher, Alexander <Alexander.Deucher@xxxxxxx>
> Subject: [PATCH 2/2] drm/amdgpu: use the same HDP flush registers for all nbio
> 2.3.x
>
> Align RDNA2.x with other asics. One HDP bit per SDMA instance,
> aligned with firmware. This is effectively a revert of
> commit 369b7d04baf3 ("drm/amdgpu/nbio2.3: don't use GPU_HDP_FLUSH bit
> 12").
> On further discussions with the relevant hardware teams,
> re-align the bits for SDMA.
>
> Signed-off-by: Alex Deucher <alexander.deucher@xxxxxxx>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 5 +----
> drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c | 21 -------------------
> drivers/gpu/drm/amd/amdgpu/nbio_v2_3.h | 1 -
> 3 files changed, 1 insertion(+), 26 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> index 4f83897a54a8..22144ba6c7ec 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> @@ -2229,15 +2229,12 @@ int amdgpu_discovery_set_ip_blocks(struct
> amdgpu_device *adev)
> case IP_VERSION(2, 3, 0):
> case IP_VERSION(2, 3, 1):
> case IP_VERSION(2, 3, 2):
> - adev->nbio.funcs = &nbio_v2_3_funcs;
> - adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg;
> - break;
> case IP_VERSION(3, 3, 0):
> case IP_VERSION(3, 3, 1):
> case IP_VERSION(3, 3, 2):
> case IP_VERSION(3, 3, 3):
> adev->nbio.funcs = &nbio_v2_3_funcs;
> - adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg_sc;
> + adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg;
> break;
> case IP_VERSION(4, 3, 0):
> case IP_VERSION(4, 3, 1):
> diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
> b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
> index 34c610b9157d..b465baa26762 100644
> --- a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
> +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
> @@ -328,27 +328,6 @@ const struct nbio_hdp_flush_reg
> nbio_v2_3_hdp_flush_reg = {
> .ref_and_mask_sdma1 =
> BIF_BX_PF_GPU_HDP_FLUSH_DONE__SDMA1_MASK,
> };
>
> -const struct nbio_hdp_flush_reg nbio_v2_3_hdp_flush_reg_sc = {
> - .ref_and_mask_cp0 =
> BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP0_MASK,
> - .ref_and_mask_cp1 =
> BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP1_MASK,
> - .ref_and_mask_cp2 =
> BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP2_MASK,
> - .ref_and_mask_cp3 =
> BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP3_MASK,
> - .ref_and_mask_cp4 =
> BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP4_MASK,
> - .ref_and_mask_cp5 =
> BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP5_MASK,
> - .ref_and_mask_cp6 =
> BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP6_MASK,
> - .ref_and_mask_cp7 =
> BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP7_MASK,
> - .ref_and_mask_cp8 =
> BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP8_MASK,
> - .ref_and_mask_cp9 =
> BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP9_MASK,
> - .ref_and_mask_sdma0 = GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK,
> - .ref_and_mask_sdma1 = GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK,
> - .ref_and_mask_sdma2 = GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK,
> - .ref_and_mask_sdma3 = GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK,
> - .ref_and_mask_sdma4 = GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK,
> - .ref_and_mask_sdma5 = GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK,
> - .ref_and_mask_sdma6 = GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK,
> - .ref_and_mask_sdma7 = GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK,
> -};
> -
> static void nbio_v2_3_init_registers(struct amdgpu_device *adev)
> {
> uint32_t def, data;
> diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.h
> b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.h
> index 6074dd3a1ed8..a43b60acf7f6 100644
> --- a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.h
> +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.h
> @@ -27,7 +27,6 @@
> #include "soc15_common.h"
>
> extern const struct nbio_hdp_flush_reg nbio_v2_3_hdp_flush_reg;
> -extern const struct nbio_hdp_flush_reg nbio_v2_3_hdp_flush_reg_sc;
> extern const struct amdgpu_nbio_funcs nbio_v2_3_funcs;
>
> #endif
> --
> 2.35.3
