Reviewed-by: Guchun Chen <guchun.chen@xxxxxxx>
Regards,
Guchun
-----Original Message-----
From: amd-gfx <amd-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx> On Behalf Of Alex Deucher
Sent: Wednesday, June 1, 2022 5:13 AM
To: Deucher, Alexander <Alexander.Deucher@xxxxxxx>
Cc: amd-gfx list <amd-gfx@xxxxxxxxxxxxxxxxxxxxx>
Subject: Re: [PATCH] drm/amdgpu: convert sienna_cichlid_populate_umd_state_clk() to use IP version
Ping?
On Tue, May 24, 2022 at 10:09 PM Alex Deucher <alexander.deucher@xxxxxxx> wrote:
>
> Rather than asic type.
>
> Signed-off-by: Alex Deucher <alexander.deucher@xxxxxxx>
> ---
> .../gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 10 +++++-----
> 1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> index 78f3d9e722bb..871435cca3c1 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> @@ -1464,19 +1464,19 @@ static int sienna_cichlid_populate_umd_state_clk(struct smu_context *smu)
> pstate_table->socclk_pstate.min = soc_table->min;
> pstate_table->socclk_pstate.peak = soc_table->max;
>
> - switch (adev->asic_type) {
> - case CHIP_SIENNA_CICHLID:
> - case CHIP_NAVY_FLOUNDER:
> + switch (adev->ip_versions[MP1_HWIP][0]) {
> + case IP_VERSION(11, 0, 7):
> + case IP_VERSION(11, 0, 11):
> pstate_table->gfxclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_GFXCLK;
> pstate_table->uclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_MEMCLK;
> pstate_table->socclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_SOCCLK;
> break;
> - case CHIP_DIMGREY_CAVEFISH:
> + case IP_VERSION(11, 0, 12):
> pstate_table->gfxclk_pstate.standard = DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_GFXCLK;
> pstate_table->uclk_pstate.standard = DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_MEMCLK;
> pstate_table->socclk_pstate.standard = DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_SOCCLK;
> break;
> - case CHIP_BEIGE_GOBY:
> + case IP_VERSION(11, 0, 13):
> pstate_table->gfxclk_pstate.standard = BEIGE_GOBY_UMD_PSTATE_PROFILING_GFXCLK;
> pstate_table->uclk_pstate.standard = BEIGE_GOBY_UMD_PSTATE_PROFILING_MEMCLK;
> pstate_table->socclk_pstate.standard = BEIGE_GOBY_UMD_PSTATE_PROFILING_SOCCLK;
> --
> 2.35.3
>
