[AMD Official Use Only - General]
Hi Daniel
Thanks for your comments and explanations. I replied in-line and look forward to more discussion.
regards
David
From: Daniel Vetter <daniel@xxxxxxxx>
Sent: Thursday, May 12, 2022 7:22 AM
To: Alex Deucher <alexdeucher@xxxxxxxxx>
Cc: Zhang, Dingchen (David) <Dingchen.Zhang@xxxxxxx>; amd-gfx list <amd-gfx@xxxxxxxxxxxxxxxxxxxxx>; Wang, Chao-kai (Stylon) <Stylon.Wang@xxxxxxx>; Li, Sun peng (Leo) <Sunpeng.Li@xxxxxxx>; Wentland, Harry <Harry.Wentland@xxxxxxx>; Zhuo, Qingqing (Lillian) <Qingqing.Zhuo@xxxxxxx>; Siqueira, Rodrigo <Rodrigo.Siqueira@xxxxxxx>; Li, Roman <Roman.Li@xxxxxxx>; Chiu, Solomon <Solomon.Chiu@xxxxxxx>; Zuo, Jerry <Jerry.Zuo@xxxxxxx>; Pillai, Aurabindo <Aurabindo.Pillai@xxxxxxx>; Lin, Wayne <Wayne.Lin@xxxxxxx>; Lakha, Bhawanpreet <Bhawanpreet.Lakha@xxxxxxx>; Gutierrez, Agustin <Agustin.Gutierrez@xxxxxxx>; Kotarac, Pavle <Pavle.Kotarac@xxxxxxx>
Subject: Re: [PATCH v2 00/19] DC/DM changes needed for amdgpu PSR-SU
On Wed, 11 May 2022 at 17:35, Alex Deucher <alexdeucher@xxxxxxxxx> wrote:
On Tue, May 10, 2022 at 4:45 PM David Zhang <dingchen.zhang@xxxxxxx> wrote:
changes in v2:
-----------------------
- set vsc_packet_rev2 for PSR1 which is safer
- add exposure of AMD specific DPCD regs for PSR-SU-RC (rate-control)
- add DC/DM change related to amdgpu PSR-SU-RC
David Zhang (18):
drm/amd/display: align dmub cmd header to latest dmub FW to support
PSR-SU
drm/amd/display: feed PSR-SU as psr version to dmub FW
drm/amd/display: combine dirty rectangles in DMUB FW
drm/amd/display: update GSP1 generic info packet for PSRSU
drm/amd/display: revise Start/End SDP data
drm/amd/display: program PSR2 DPCD Configuration
drm/amd/display: Passing Y-granularity to dmub fw
drm/amd/display: Set default value of line_capture_indication
drm/amd/display: add vline time in micro sec to PSR context
drm/amd/display: fix system hang when PSR exits
drm/amd/display: Set PSR level to enable ALPM by default
drm/amd/display: use HW lock mgr for PSR-SU
drm/amd/display: PSRSU+DSC WA for specific TCON
drm/amd/display: add shared helpers to update psr config fields to
power module
drm/amd/display: calculate psr config settings in runtime in DM
drm/amd/display: update cursor position to DMUB FW
drm/amd/display: expose AMD source specific DPCD for FreeSync PSR
support
drm/amd/display: PSR-SU rate control support in DC
Leo Li (1):
drm/amd/display: Implement MPO PSR SU
A couple of suggestions from Daniel on IRC:
1. Might be good to extract the "calculate total crtc damage" code
from i915 in intel_psr2_sel_fetch_update, stuff that into damage
helpers and reuse for i915 and amdgpu
To expand a bit on this. There is currently a helper for total damage,
but it's at the fb/plane level for drivers which need to upload
buffers (usb/spi or virtual) drm_atomic_helper_damage_merged(). That
one probably needs to be renamed to signify it's about the plane, and
then we need a new drm_atomic_helper_crtc_damage_merged() which
(extract from i915 code ideally) which computes total crtc damage for
stuff like psr2/su or the command mode dsi panels (unfortunately none
of the drivers for android for these panels have been upstreamed yet).
<<<
Checked the DRM comment for the helper `drm_atomic_helper_damage_merged()` and
quoted below:
*****
Drivers might want to use the helper functions drm_atomic_helper_damage_iter_init()
and drm_atomic_helper_damage_iter_next() or drm_atomic_helper_damage_merged()
if the driver can only handle a single damage region at most.
*****
Currently for amdgpu, the multiple damage clips combination (merging) is handled in
DMUB firmware. And the DRM comment shows that the usage of "damage_merged()"
helper is for the driver which can only handle single damage region at most.
Since AMDGPU is capable of handling multiple damaged clip (in DMUB FW), can I
understand that the group of helpers of `damage_merged()` in DRM is not mandatory
but optional?
