Managing power profiles mode is not allowed in SRIOV mode for Sienna Cichlid.
This patch is adjusting the "pp_power_profile_mode" and
"power_dpm_force_performance_level" accordingly.
Signed-off-by: Danijel Slivka <danijel.slivka@xxxxxxx>
---
drivers/gpu/drm/amd/pm/amdgpu_pm.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
index 70a0aad05426..59a662aeaaf3 100644
--- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
@@ -2025,6 +2025,8 @@ static int default_attr_update(struct amdgpu_device *adev, struct amdgpu_device_
} else if (DEVICE_ATTR_IS(pp_power_profile_mode)) {
if (amdgpu_dpm_get_power_profile_mode(adev, NULL) == -EOPNOTSUPP)
*states = ATTR_STATE_UNSUPPORTED;
+ else if (gc_ver == IP_VERSION(10, 3, 0) && amdgpu_sriov_vf(adev))
+ *states = ATTR_STATE_UNSUPPORTED;
}
switch (gc_ver) {
@@ -2038,6 +2040,13 @@ static int default_attr_update(struct amdgpu_device *adev, struct amdgpu_device_
dev_attr->store = NULL;
}
break;
+ case IP_VERSION(10, 3, 0):
+ if (DEVICE_ATTR_IS(power_dpm_force_performance_level) &&
+ amdgpu_sriov_vf(adev)) {
+ dev_attr->attr.mode &= ~S_IWUGO;
+ dev_attr->store = NULL;
+ }
+ break;
default:
break;
}
--
2.25.1
