Re: [PATCH v2] drm/amdgpu: Ensure the DMA engine is deactivated during set ups

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On Wed, Apr 27, 2022 at 8:31 AM <ricetons@xxxxxxxxx> wrote:
>
> From: Haohui Mai <haohui@xxxxxxxxxxxx>
>
> The patch fully deactivates the DMA engine before setting up the ring
> buffer to avoid potential data races and crashes.
>
> Signed-off-by: Haohui Mai <haohui@xxxxxxxxxxxx>
> ---
>  drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 94 ++++++++++++++------------
>  1 file changed, 50 insertions(+), 44 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
> index 013d2dec81d0..cb3987dd3bda 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
> @@ -459,7 +459,6 @@ static void sdma_v5_2_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 se
>         }
>  }
>
> -
>  /**
>   * sdma_v5_2_gfx_stop - stop the gfx async dma engines
>   *
> @@ -505,17 +504,19 @@ static void sdma_v5_2_rlc_stop(struct amdgpu_device *adev)
>  }
>
>  /**
> - * sdma_v5_2_ctx_switch_enable - stop the async dma engines context switch
> + * sdma_v5_2_ctx_switch_enable_for_instance - start the async dma engines
> + * context switch for an instance
>   *
>   * @adev: amdgpu_device pointer
> - * @enable: enable/disable the DMA MEs context switch.
> + * @i: the index of the SDMA instance
>   *
> - * Halt or unhalt the async dma engines context switch.
> + * Unhalt the async dma engines context switch.
>   */
> -static void sdma_v5_2_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
> +static void sdma_v5_2_ctx_switch_enable_for_instance(struct amdgpu_device *adev, int i)
>  {
>         u32 f32_cntl, phase_quantum = 0;
> -       int i;
> +
> +       WARN_ON(i >= adev->sdma.num_instances);
>
>         if (amdgpu_sdma_phase_quantum) {
>                 unsigned value = amdgpu_sdma_phase_quantum;
> @@ -539,26 +540,44 @@ static void sdma_v5_2_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
>                 phase_quantum =
>                         value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT |
>                         unit  << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT;
> -       }
>
> -       for (i = 0; i < adev->sdma.num_instances; i++) {
> -               if (enable && amdgpu_sdma_phase_quantum) {
> -                       WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM),
> -                              phase_quantum);
> -                       WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM),
> -                              phase_quantum);
> -                       WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM),
> -                              phase_quantum);
> -               }
> +               WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM),
> +                      phase_quantum);
> +               WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM),
> +                      phase_quantum);
> +               WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM),
> +                      phase_quantum);
> +       }
>
> -               if (!amdgpu_sriov_vf(adev)) {
> -                       f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL));
> -                       f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
> -                                       AUTO_CTXSW_ENABLE, enable ? 1 : 0);
> -                       WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl);
> -               }
> +       if (!amdgpu_sriov_vf(adev)) {
> +               f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL));
> +               f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
> +                               AUTO_CTXSW_ENABLE, 1);
> +               WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl);
>         }
> +}
>
> +/**
> + * sdma_v5_2_ctx_switch_disable_all - stop the async dma engines context switch
> + *
> + * @adev: amdgpu_device pointer
> + *
> + * Halt the async dma engines context switch.
> + */
> +static void sdma_v5_2_ctx_switch_disable_all(struct amdgpu_device *adev)
> +{
> +       u32 f32_cntl;
> +       int i;
> +
> +       if (amdgpu_sriov_vf(adev))
> +               return;
> +
> +       for (i = 0; i < adev->sdma.num_instances; i++) {
> +               f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL));
> +               f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
> +                               AUTO_CTXSW_ENABLE, 0);
> +               WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl);
> +       }
>  }
>
>  /**
> @@ -571,21 +590,10 @@ static void sdma_v5_2_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
>   */
>  static void sdma_v5_2_enable(struct amdgpu_device *adev, bool enable)
>  {
> -       u32 f32_cntl;
> -       int i;
> -
>         if (!enable) {
>                 sdma_v5_2_gfx_stop(adev);
>                 sdma_v5_2_rlc_stop(adev);
>         }
> -
> -       if (!amdgpu_sriov_vf(adev)) {
> -               for (i = 0; i < adev->sdma.num_instances; i++) {
> -                       f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
> -                       f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);
> -                       WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl);
> -               }
> -       }

As this function no longer provides a way to enable anything, better
to rename it to something like sdma_v5_2_halt() and drop the enable
parameter.

Alex

>  }
>
>  /**
> @@ -594,6 +602,9 @@ static void sdma_v5_2_enable(struct amdgpu_device *adev, bool enable)
>   * @adev: amdgpu_device pointer
>   *
>   * Set up the gfx DMA ring buffers and enable them.
> + * It assumes that the dma engine is stopped for each instance.
> + * The function enables the engine and preemptions sequentially for each instance.
> + *
>   * Returns 0 for success, error for failure.
>   */
>  static int sdma_v5_2_gfx_resume(struct amdgpu_device *adev)
> @@ -737,10 +748,7 @@ static int sdma_v5_2_gfx_resume(struct amdgpu_device *adev)
>
>                 ring->sched.ready = true;
>
> -               if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */
> -                       sdma_v5_2_ctx_switch_enable(adev, true);
> -                       sdma_v5_2_enable(adev, true);
> -               }
> +               sdma_v5_2_ctx_switch_enable_for_instance(adev, i);
>
>                 r = amdgpu_ring_test_ring(ring);
>                 if (r) {
> @@ -856,7 +864,7 @@ static int sdma_v5_2_start(struct amdgpu_device *adev)
>         int r = 0;
>
>         if (amdgpu_sriov_vf(adev)) {
> -               sdma_v5_2_ctx_switch_enable(adev, false);
> +               sdma_v5_2_ctx_switch_disable_all(adev);
>                 sdma_v5_2_enable(adev, false);
>
>                 /* set RB registers */
> @@ -881,12 +889,10 @@ static int sdma_v5_2_start(struct amdgpu_device *adev)
>                 amdgpu_gfx_off_ctrl(adev, false);
>
>         sdma_v5_2_soft_reset(adev);
> -       /* unhalt the MEs */
> -       sdma_v5_2_enable(adev, true);
> -       /* enable sdma ring preemption */
> -       sdma_v5_2_ctx_switch_enable(adev, true);
>
> -       /* start the gfx rings and rlc compute queues */
> +       /* Soft reset supposes to disable the dma engine and preemption.
> +        * Now start the gfx rings and rlc compute queues.
> +        */
>         r = sdma_v5_2_gfx_resume(adev);
>         if (adev->in_s0ix)
>                 amdgpu_gfx_off_ctrl(adev, true);
> @@ -1340,7 +1346,7 @@ static int sdma_v5_2_hw_fini(void *handle)
>         if (amdgpu_sriov_vf(adev))
>                 return 0;
>
> -       sdma_v5_2_ctx_switch_enable(adev, false);
> +       sdma_v5_2_ctx_switch_disable_all(adev);
>         sdma_v5_2_enable(adev, false);
>
>         return 0;
> --
> 2.25.1
>



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