[AMD Official Use Only]
Reviewed-by: Evan Quan <evan.quan@xxxxxxx>
> -----Original Message-----
> From: Chen, Guchun <Guchun.Chen@xxxxxxx>
> Sent: Friday, April 22, 2022 5:47 PM
> To: amd-gfx@xxxxxxxxxxxxxxxxxxxxx; Koenig, Christian
> <Christian.Koenig@xxxxxxx>; Zhang, Hawking <Hawking.Zhang@xxxxxxx>;
> Deucher, Alexander <Alexander.Deucher@xxxxxxx>; Lazar, Lijo
> <Lijo.Lazar@xxxxxxx>; Quan, Evan <Evan.Quan@xxxxxxx>
> Cc: Chen, Guchun <Guchun.Chen@xxxxxxx>
> Subject: [PATCH] drm/amdgpu: control baco sequence by driver on several
> SIENNA_CICHLID SKUs
>
> Add a quirk to switch baco trigger sequence from armd3 sequence
> to control by driver itself on several SKUs, otherwise, SMU will
> fail to be resumed from runtime suspend. Will drop this after a
> clean solution between kernel driver and SMU FW is available.
>
> amdgpu 0000:63:00.0: amdgpu: GECC is enabled
> amdgpu 0000:63:00.0: amdgpu: SECUREDISPLAY: securedisplay ta ucode is
> not available
> amdgpu 0000:63:00.0: amdgpu: SMU is resuming...
> amdgpu 0000:63:00.0: amdgpu: SMU: I'm not done with your command:
> SMN_C2PMSG_66:0x0000000E SMN_C2PMSG_82:0x00000080
> amdgpu 0000:63:00.0: amdgpu: Failed to SetDriverDramAddr!
> amdgpu 0000:63:00.0: amdgpu: Failed to setup smc hw!
> [drm:amdgpu_device_ip_resume_phase2 [amdgpu]] *ERROR* resume of IP
> block <smu> failed -62
> amdgpu 0000:63:00.0: amdgpu: amdgpu_device_ip_resume failed (-62)
>
> Signed-off-by: Guchun Chen <guchun.chen@xxxxxxx>
> ---
> .../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 19
> +++++++++++++++++--
> 1 file changed, 17 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> index b7320ecf4934..494a42c253d8 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> @@ -2246,11 +2246,25 @@ static int sienna_cichlid_run_btc(struct
> smu_context *smu)
> return res;
> }
>
> +static bool sienna_cichlid_baco_trigger_quirk(struct amdgpu_device *adev)
> +{
> + /*
> + * Add this quirk on several SKUs to control baco enter/exit by
> + * driver instead of trigger baco via BACO_SEQ_BACO in armd3
> sequence.
> + */
> + if (((adev->pdev->device == 0x73A1) && (adev->pdev->revision ==
> 0x00)) ||
> + ((adev->pdev->device == 0x73BF) && (adev->pdev->revision ==
> 0xCF)))
> + return true;
> + else
> + return false;
> +}
> +
> static int sienna_cichlid_baco_enter(struct smu_context *smu)
> {
> struct amdgpu_device *adev = smu->adev;
>
> - if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev))
> + if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev) &&
> + !sienna_cichlid_baco_trigger_quirk(adev))
> return smu_v11_0_baco_set_armd3_sequence(smu,
> BACO_SEQ_BACO);
> else
> return smu_v11_0_baco_enter(smu);
> @@ -2260,7 +2274,8 @@ static int sienna_cichlid_baco_exit(struct
> smu_context *smu)
> {
> struct amdgpu_device *adev = smu->adev;
>
> - if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev)) {
> + if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev) &&
> + !sienna_cichlid_baco_trigger_quirk(adev)) {
> /* Wait for PMFW handling for the Dstate change */
> msleep(10);
> return smu_v11_0_baco_set_armd3_sequence(smu,
> BACO_SEQ_ULPS);
> --
> 2.17.1
