[AMD Official Use Only]
> -----Original Message-----
> From: Alex Deucher <alexdeucher@xxxxxxxxx>
> Sent: Tuesday, March 29, 2022 11:28 AM
> To: Russell, Kent <Kent.Russell@xxxxxxx>
> Cc: amd-gfx list <amd-gfx@xxxxxxxxxxxxxxxxxxxxx>
> Subject: Re: [PATCH 4/4] drm/amdgpu: Add unique_id support for sienna cichlid
>
> On Tue, Mar 29, 2022 at 11:10 AM Kent Russell <kent.russell@xxxxxxx> wrote:
> >
> > This is being added to SMU Metrics, so add the required tie-ins in the
> > kernel. Also create the corresponding unique_id sysfs file.
> >
> > v2: Add FW version check, remove SMU mutex
> > v3: Fix style warning
> > v4: Add MP1 IP_VERSION check to FW version check
> >
> > Signed-off-by: Kent Russell <kent.russell@xxxxxxx>
> > ---
> > drivers/gpu/drm/amd/pm/amdgpu_pm.c | 1 +
> > .../pmfw_if/smu11_driver_if_sienna_cichlid.h | 13 ++++++--
> > .../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 33 +++++++++++++++++++
> > 3 files changed, 45 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
> b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
> > index 4151db2678fb..4a9aabc16fbc 100644
> > --- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
> > +++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
> > @@ -1993,6 +1993,7 @@ static int default_attr_update(struct amdgpu_device *adev,
> struct amdgpu_device_
> > case IP_VERSION(9, 4, 0):
> > case IP_VERSION(9, 4, 1):
> > case IP_VERSION(9, 4, 2):
> > + case IP_VERSION(10, 3, 0):
> > *states = ATTR_STATE_SUPPORTED;
> > break;
> > default:
> > diff --git
> a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h
> b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h
> > index 3e4a314ef925..5831145646e6 100644
> > --- a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h
> > +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h
> > @@ -1419,8 +1419,11 @@ typedef struct {
> > uint8_t PcieRate ;
> > uint8_t PcieWidth ;
> > uint16_t AverageGfxclkFrequencyTarget;
> > - uint16_t Padding16_2;
> >
> > + uint32_t PublicSerialNumLower32;
> > + uint32_t PublicSerialNumUpper32;
> > +
> > + uint16_t Padding16_2;
> > } SmuMetrics_t;
> >
> > typedef struct {
> > @@ -1476,8 +1479,11 @@ typedef struct {
> > uint8_t PcieRate ;
> > uint8_t PcieWidth ;
> > uint16_t AverageGfxclkFrequencyTarget;
> > - uint16_t Padding16_2;
> >
> > + uint32_t PublicSerialNumLower32;
> > + uint32_t PublicSerialNumUpper32;
> > +
> > + uint16_t Padding16_2;
> > } SmuMetrics_V2_t;
> >
> > typedef struct {
> > @@ -1535,6 +1541,9 @@ typedef struct {
> > uint8_t PcieWidth;
> > uint16_t AverageGfxclkFrequencyTarget;
> >
> > + uint32_t PublicSerialNumLower32;
> > + uint32_t PublicSerialNumUpper32;
> > +
> > } SmuMetrics_V3_t;
> >
>
> Was this really added to all three versions of the metrics table? If
> it's a new addition, presumably it's only in v3? Other than that, the
> series is:
> Reviewed-by: Alex Deucher <alexander.deucher@xxxxxxx>
Apparently it was. I checked with the PMFW dev and he said it was there, so I'm trusting him on that one. Thanks for the reviews!
Kent
>
> Alex
>
> > typedef struct {
> > diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> > index 38f04836c82f..b2f3d80e5945 100644
> > --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> > +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> > @@ -715,6 +715,16 @@ static int sienna_cichlid_get_smu_metrics_data(struct
> smu_context *smu,
> > *value = use_metrics_v3 ? metrics_v3->CurrFanSpeed :
> > use_metrics_v2 ? metrics_v2->CurrFanSpeed : metrics->CurrFanSpeed;
> > break;
> > + case METRICS_UNIQUE_ID_UPPER32:
> > + *value = use_metrics_v3 ? metrics_v3->PublicSerialNumUpper32 :
> > + use_metrics_v2 ? metrics_v2->PublicSerialNumUpper32 :
> > + metrics->PublicSerialNumUpper32;
> > + break;
> > + case METRICS_UNIQUE_ID_LOWER32:
> > + *value = use_metrics_v3 ? metrics_v3->PublicSerialNumLower32 :
> > + use_metrics_v2 ? metrics_v2->PublicSerialNumLower32 :
> > + metrics->PublicSerialNumLower32;
> > + break;
> > default:
> > *value = UINT_MAX;
> > break;
> > @@ -1773,6 +1783,28 @@ static int sienna_cichlid_read_sensor(struct smu_context
> *smu,
> > return ret;
> > }
> >
> > +static void sienna_cichlid_get_unique_id(struct smu_context *smu)
> > +{
> > + struct amdgpu_device *adev = smu->adev;
> > + uint32_t upper32 = 0, lower32 = 0;
> > +
> > + /* Only supported as of version 0.58.83.0 and only on Sienna Cichlid */
> > + if (smu->smc_fw_version < 0x3A5300 ||
> > + smu->adev->ip_versions[MP1_HWIP][0] != IP_VERSION(11, 0, 7))
> > + return;
> > +
> > + if (sienna_cichlid_get_smu_metrics_data(smu, METRICS_UNIQUE_ID_UPPER32,
> &upper32))
> > + goto out;
> > + if (sienna_cichlid_get_smu_metrics_data(smu, METRICS_UNIQUE_ID_LOWER32,
> &lower32))
> > + goto out;
> > +
> > +out:
> > +
> > + adev->unique_id = ((uint64_t)upper32 << 32) | lower32;
> > + if (adev->serial[0] == '\0')
> > + sprintf(adev->serial, "%016llx", adev->unique_id);
> > +}
> > +
> > static int sienna_cichlid_get_uclk_dpm_states(struct smu_context *smu, uint32_t
> *clocks_in_khz, uint32_t *num_states)
> > {
> > uint32_t num_discrete_levels = 0;
> > @@ -4182,6 +4214,7 @@ static const struct pptable_funcs sienna_cichlid_ppt_funcs = {
> > .get_ecc_info = sienna_cichlid_get_ecc_info,
> > .get_default_config_table_settings =
> sienna_cichlid_get_default_config_table_settings,
> > .set_config_table = sienna_cichlid_set_config_table,
> > + .get_unique_id = sienna_cichlid_get_unique_id,
> > };
> >
> > void sienna_cichlid_set_ppt_funcs(struct smu_context *smu)
> > --
> > 2.25.1
> >
