Reviewed-by: Hersen Wu <Hersenxs.Wu@xxxxxxx>
-----Original Message-----
From: Chauhan, Ikshwaku <Ikshwaku.Chauhan@xxxxxxx>
Sent: Thursday, March 24, 2022 3:12 AM
To: Wentland, Harry <Harry.Wentland@xxxxxxx>; amd-gfx@xxxxxxxxxxxxxxxxxxxxx
Cc: Wentland, Harry <Harry.Wentland@xxxxxxx>; stable@xxxxxxxxxxxxxxx; Wu, Hersen <hersenxs.wu@xxxxxxx>; Kazlauskas, Nicholas <Nicholas.Kazlauskas@xxxxxxx>; VURDIGERENATARAJ, CHANDAN <CHANDAN.VURDIGERENATARAJ@xxxxxxx>
Subject: RE: [PATCH] drm/amd/display: Program color range and encoding correctly for DCN2+
[AMD Official Use Only]
Tested-by: Ikshwaku.chauhan@xxxxxxx
Thanks,
Ikshwaku Chauhan
-----Original Message-----
From: Harry Wentland <harry.wentland@xxxxxxx>
Sent: Thursday, March 24, 2022 2:39 AM
To: amd-gfx@xxxxxxxxxxxxxxxxxxxxx
Cc: Wentland, Harry <Harry.Wentland@xxxxxxx>; stable@xxxxxxxxxxxxxxx; Wu, Hersen <hersenxs.wu@xxxxxxx>; Chauhan, Ikshwaku <Ikshwaku.Chauhan@xxxxxxx>; Kazlauskas, Nicholas <Nicholas.Kazlauskas@xxxxxxx>; VURDIGERENATARAJ, CHANDAN <CHANDAN.VURDIGERENATARAJ@xxxxxxx>
Subject: [PATCH] drm/amd/display: Program color range and encoding correctly for DCN2+
[Why]
DCN2 CNVC programming did not respect the input_color_space and was therefore programming the wrong CSC matrix for YUV to RGB conversion, leading to a wrong image. In particular blacks for limited range videos would show as dark grey.
[How]
Do what DCN1 does and use the input_color_space info in dpp_setup if it's available.
Signed-off-by: Harry Wentland <harry.wentland@xxxxxxx>
Cc: stable@xxxxxxxxxxxxxxx
Cc: hersenxs.wu@xxxxxxx
Cc: Ikshwaku.Chauhan@xxxxxxx
Cc: Nicholas.Kazlauskas@xxxxxxx
Cc: CHANDAN.VURDIGERENATARAJ@xxxxxxx
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c | 3 +++
drivers/gpu/drm/amd/display/dc/dcn201/dcn201_dpp.c | 3 +++
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c | 3 +++
3 files changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c
index 970b65efeac1..eaa7032f0f1a 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c
@@ -212,6 +212,9 @@ static void dpp2_cnv_setup (
break;
}
+ /* Set default color space based on format if none is given. */
+ color_space = input_color_space ? input_color_space : color_space;
+
if (is_2bit == 1 && alpha_2bit_lut != NULL) {
REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT0, alpha_2bit_lut->lut0);
REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT1, alpha_2bit_lut->lut1); diff --git a/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_dpp.c b/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_dpp.c
index 8b6505b7dca8..f50ab961bc17 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_dpp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_dpp.c
@@ -153,6 +153,9 @@ static void dpp201_cnv_setup(
break;
}
+ /* Set default color space based on format if none is given. */
+ color_space = input_color_space ? input_color_space : color_space;
+
if (is_2bit == 1 && alpha_2bit_lut != NULL) {
REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT0, alpha_2bit_lut->lut0);
REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT1, alpha_2bit_lut->lut1); diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c
index ab3918c0a15b..0dcc07531643 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c
@@ -294,6 +294,9 @@ static void dpp3_cnv_setup (
break;
}
+ /* Set default color space based on format if none is given. */
+ color_space = input_color_space ? input_color_space : color_space;
+
if (is_2bit == 1 && alpha_2bit_lut != NULL) {
REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT0, alpha_2bit_lut->lut0);
REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT1, alpha_2bit_lut->lut1);
--
2.35.1
