Regards,
Lang
> Regards,
> Christian.
>
> > +
> > + return r;
> > +}
> > +
> > +static int vcn_v1_0_ring_patch_cs_in_place(struct amdgpu_cs_parser *p,
> > + struct amdgpu_job *job,
> > + struct amdgpu_ib *ib)
> > +{
> > + uint32_t msg_lo = 0, msg_hi = 0;
> > + int i, r;
> > +
> > + for (i = 0; i < ib->length_dw; i += 2) {
> > + uint32_t reg = amdgpu_ib_get_value(ib, i);
> > + uint32_t val = amdgpu_ib_get_value(ib, i + 1);
> > +
> > + if (reg == PACKET0(p->adev->vcn.internal.data0, 0)) {
> > + msg_lo = val;
> > + } else if (reg == PACKET0(p->adev->vcn.internal.data1, 0)) {
> > + msg_hi = val;
> > + } else if (reg == PACKET0(p->adev->vcn.internal.cmd, 0)) {
> > + r = vcn_v1_0_validate_bo(p, job,
> > + ((u64)msg_hi) << 32 | msg_lo);
> > + if (r)
> > + return r;
> > + }
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +
> > static const struct amdgpu_ring_funcs vcn_v1_0_dec_ring_vm_funcs = {
> > .type = AMDGPU_RING_TYPE_VCN_DEC,
> > .align_mask = 0xf,
> > @@ -1914,6 +1981,7 @@ static const struct amdgpu_ring_funcs vcn_v1_0_dec_ring_vm_funcs = {
> > .get_rptr = vcn_v1_0_dec_ring_get_rptr,
> > .get_wptr = vcn_v1_0_dec_ring_get_wptr,
> > .set_wptr = vcn_v1_0_dec_ring_set_wptr,
> > + .patch_cs_in_place = vcn_v1_0_ring_patch_cs_in_place,
> > .emit_frame_size =
> > 6 + 6 + /* hdp invalidate / flush */
> > SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
>
