[AMD Official Use Only]
Reviewed-by: Huang Rui <ray.huang@xxxxxxx>
-----Original Message-----
From: Zhang, Yifan <Yifan1.Zhang@xxxxxxx>
Sent: Monday, March 7, 2022 3:54 PM
To: amd-gfx@xxxxxxxxxxxxxxxxxxxxx
Cc: Deucher, Alexander <Alexander.Deucher@xxxxxxx>; Huang, Ray <Ray.Huang@xxxxxxx>; Zhang, Yifan <Yifan1.Zhang@xxxxxxx>
Subject: [PATCH 1/2] drm/amdgpu: change registers in error checking for smu 13.0.5
smu 13.0.5 use new registers for smu msg and param.
Signed-off-by: Yifan Zhang <yifan1.zhang@xxxxxxx>
---
drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
index 590a6ed12d54..89b22b261066 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
@@ -160,11 +160,17 @@ static void __smu_cmn_reg_print_error(struct smu_context *smu, {
struct amdgpu_device *adev = smu->adev;
const char *message = smu_get_message_name(smu, msg);
+ u32 msg_idx, prm;
switch (reg_c2pmsg_90) {
case SMU_RESP_NONE: {
- u32 msg_idx = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66);
- u32 prm = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82);
+ if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 5)) {
+ msg_idx = RREG32_SOC15(MP1, 0, mmMP1_C2PMSG_2);
+ prm = RREG32_SOC15(MP1, 0, mmMP1_C2PMSG_34);
+ } else {
+ msg_idx = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66);
+ prm = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82);
+ }
dev_err_ratelimited(adev->dev,
"SMU: I'm not done with your previous command: SMN_C2PMSG_66:0x%08X SMN_C2PMSG_82:0x%08X",
msg_idx, prm);
--
2.25.1
